Skip to content

Commit f7bc645

Browse files
AMATHamathxbt
authored andcommitted
fix(air): update tests and CHANGELOG for memory addr range check
- Update build_trace_row() test helper to populate ADDR_LO_COL_IDX and ADDR_HI_COL_IDX columns so that verify_memory_access() comparisons remain correct now that fill_trace() writes these two new witness columns. - Import ADDR_HI_COL_IDX and ADDR_LO_COL_IDX in the test module. - Add CHANGELOG entry under v0.23.0 Bug Fixes.
1 parent e6d815c commit f7bc645

File tree

2 files changed

+12
-3
lines changed

2 files changed

+12
-3
lines changed

CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44

55
#### Bug Fixes
66

7+
- Fixed a proof-soundness vulnerability in the memory chiplet AIR: `word_addr` was never constrained to `[0, 2^32)`, allowing a dishonest prover to supply arbitrary field elements as memory addresses. The fix commits to two 16-bit witness columns (`addr_lo`, `addr_hi`) and enforces a reconstruction constraint plus range checks via the existing range-check bus ([#2935](https://github.com/0xMiden/miden-vm/pull/2935)).
78
- Reverted `InvokeKind::ProcRef` back to `InvokeKind::Exec` in `visit_mut_procref` and added an explanatory comment (#2893).
89
#### Changes
910

processor/src/trace/chiplets/memory/tests.rs

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@ use alloc::vec::Vec;
33
use miden_air::trace::{
44
RowIndex,
55
chiplets::memory::{
6-
FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX, IDX1_COL_IDX, IS_READ_COL_IDX,
7-
IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT, MEMORY_ACCESS_WORD, MEMORY_READ,
8-
MEMORY_WRITE, TRACE_WIDTH as MEMORY_TRACE_WIDTH,
6+
ADDR_HI_COL_IDX, ADDR_LO_COL_IDX, FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX,
7+
IDX1_COL_IDX, IS_READ_COL_IDX, IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT,
8+
MEMORY_ACCESS_WORD, MEMORY_READ, MEMORY_WRITE, TRACE_WIDTH as MEMORY_TRACE_WIDTH,
99
},
1010
};
1111
use miden_core::{ONE, WORD_SIZE, Word, ZERO, assert_matches, field::Field};
@@ -577,6 +577,14 @@ fn build_trace_row(
577577
row[FLAG_SAME_CONTEXT_AND_WORD] = ZERO;
578578
}
579579

580+
// Populate address limb columns matching what fill_trace() writes.
581+
// ADDR_LO = word_addr & 0xFFFF, ADDR_HI = word_addr >> 16.
582+
let word_addr_u32: u32 = word.as_canonical_u64().try_into().unwrap();
583+
let addr_lo = u16::try_from(word_addr_u32 & 0xFFFF).unwrap();
584+
let addr_hi = u16::try_from(word_addr_u32 >> 16).unwrap();
585+
row[ADDR_LO_COL_IDX] = Felt::new(addr_lo as u64);
586+
row[ADDR_HI_COL_IDX] = Felt::new(addr_hi as u64);
587+
580588
row
581589
}
582590

0 commit comments

Comments
 (0)