Skip to content

Commit 0b0f708

Browse files
author
Igor Bagnucki
committed
Fix compilation errors part 2
Signed-off-by: Igor Bagnucki <[email protected]>
1 parent f050584 commit 0b0f708

File tree

2 files changed

+132
-132
lines changed

2 files changed

+132
-132
lines changed

‎src/include/cpu/power/istep_6.h‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@ void istep_6_11(void);
88

99
#define FREQ_PB_MHZ (1866)
1010

11+
#define MASTER_PROC (1)
12+
1113
#define OCC_FW0 (0)
1214
#define OCC_FW1 (1)
1315
#define CME_ERR_NOTIFY (2)
@@ -111,28 +113,26 @@ void istep_6_11(void);
111113
#define OCC_MODIFIED_SECTION_SIZE ((OCC_OFFSET_LENGTH) + (OCC_OFFSET_FREQ))
112114
#define OCC_LENGTH (0x120000)
113115

114-
#define NUMBER_OF_EX_CHIPLETS (6)
116+
#define OCC_GPE0_SRAM_ADDRESS (0xFFF01000)
117+
#define OCC_GPE1_SRAM_ADDRESS (0xFFF10000)
115118

116-
extern void mount_part_from_pnor(const char *part_name,
117-
struct mmap_helper_region_device *mdev);
119+
#define PU_SRAM_SRBV3_SCOM (0x0006A007)
118120

119-
const chiplet_id_t EX_CHIPLETS[NUMBER_OF_EX_CHIPLETS] =
120-
{
121-
EP00_CHIPLET_ID,
122-
EP01_CHIPLET_ID,
123-
EP02_CHIPLET_ID,
124-
EP03_CHIPLET_ID,
125-
EP04_CHIPLET_ID,
126-
EP05_CHIPLET_ID
127-
};
121+
#define PU_SPIMPSS_ADC_CTRL_REG0 (0x00070000)
122+
#define PU_SPIPSS_ADC_CTRL_REG1 (0x00070001)
123+
#define PU_SPIPSS_ADC_CTRL_REG2 (0x00070002)
124+
#define PU_SPIPSS_ADC_WDATA_REG (0x00070010)
128125

129-
const uint64_t OCBCSRn_OR[4] =
130-
{
131-
PU_OCB_PIB_OCBCSR0_OR,
132-
PU_OCB_PIB_OCBCSR1_OR,
133-
PU_OCB_PIB_OCBCSR2_OR,
134-
PU_OCB_PIB_OCBCSR3_OR
135-
};
126+
#define PU_SPIPSS_P2S_CTRL_REG0 (0x00070040)
127+
#define PU_SPIPSS_P2S_CTRL_REG1 (0x00070041)
128+
#define PU_SPIPSS_P2S_CTRL_REG2 (0x00070042)
129+
#define PU_SPIPSS_P2S_WDATA_REG (0x00070050)
130+
131+
#define PU_SPIPSS_100NS_REG (0x00070028)
132+
133+
134+
extern void mount_part_from_pnor(const char *part_name,
135+
struct mmap_helper_region_device *mdev);
136136

137137
const uint64_t PBA_BARs[4] =
138138
{

‎src/soc/ibm/power9/istep_6_11.c‎

Lines changed: 113 additions & 113 deletions
Original file line numberDiff line numberDiff line change
@@ -137,47 +137,6 @@ static void loadOCCImageDuringIpl(void* occ_bootloader)
137137
gpe_1_length);
138138
}
139139

140-
static void startOCCFromSRAM(TARGETING::Target* i_proc)
141-
{
142-
// executed only for master processor!!!
143-
if(master_proc)
144-
{
145-
pm_pss_init();
146-
}
147-
148-
pm_occ_fir_init();
149-
// executed only for master processor!!!
150-
if(master_proc)
151-
{
152-
clear_occ_special_wakeups();
153-
}
154-
155-
write_scom(PU_OCB_OCI_OIRR0A_SCOM, 0x218780f800000000);
156-
write_scom(PU_OCB_OCI_OIRR1A_SCOM, 0x0003d03c00000000);
157-
write_scom(PU_OCB_OCI_OIRR0B_SCOM, 0x2181801800000000);
158-
write_scom(PU_OCB_OCI_OIRR1B_SCOM, 0x0003d00c00000000);
159-
write_scom(PU_OCB_OCI_OIRR0C_SCOM, 0x010280ac00000000);
160-
write_scom(PU_OCB_OCI_OIRR1C_SCOM, 0x0001901400000000);
161-
162-
// executed only for master processor!!!
163-
if(master_proc)
164-
{
165-
p9_pm_occ_control(
166-
makeStart405Instruction());
167-
}
168-
169-
write_scom(OCB_OITR0, 0xffffffffffffffff);
170-
write_scom(OCB_OIEPR0, 0xffffffffffffffff);
171-
}
172-
173-
static void p9_pm_occ_control(const uint64_t i_ppc405_jump_to_main_instr)
174-
{
175-
write_scom(PU_SRAM_SRBV3_SCOM, i_ppc405_jump_to_main_instr);
176-
write_scom(PU_JTG_PIB_OJCFG_AND, ~PPC_BIT(JTG_PIB_OJCFG_DBG_HALT_BIT));
177-
write_scom(PU_OCB_PIB_OCR_OR, PPC_BIT(OCB_PIB_OCR_CORE_RESET_BIT));
178-
write_scom(PU_OCB_PIB_OCR_CLEAR, PPC_BIT(OCB_PIB_OCR_CORE_RESET_BIT));
179-
}
180-
181140
static void pm_pss_init(void)
182141
{
183142
write_scom(
@@ -203,8 +162,8 @@ static void pm_pss_init(void)
203162
| PPC_BIT(2));
204163
write_scom(
205164
PU_SPIPSS_P2S_CTRL_REG1,
206-
read_scom(PU_SPIPSS_P2S_CTRL_REG1)
207-
& ~PPC_BITMASK(1, 3)
165+
(read_scom(PU_SPIPSS_P2S_CTRL_REG1)
166+
& ~PPC_BITMASK(1, 3))
208167
| PPC_BIT(0) | PPC_BIT(10)
209168
| PPC_BIT(12) | PPC_BIT(17));
210169
write_scom(
@@ -216,7 +175,117 @@ static void pm_pss_init(void)
216175
write_scom(
217176
PU_SPIPSS_100NS_REG,
218177
(read_scom(PU_SPIPSS_100NS_REG) & 0xFFFFFFFF)
219-
| (FREQ_PB_MHZ / 40) << 32);
178+
| (uint64_t)(FREQ_PB_MHZ / 40) << 32);
179+
}
180+
181+
static void pm_occ_fir_init(void)
182+
{
183+
uint64_t iv_mask = read_scom(iv_mask_address);
184+
185+
write_scom(iv_proc, iv_fir_address, 0);
186+
write_scom(iv_proc, iv_action0_address, C405_ECC_UE);
187+
write_scom(
188+
iv_proc,
189+
iv_action1_address,
190+
C405_ECC_CE | C405_OCI_MC_CHK
191+
| C405DCU_M_TIMEOUT | GPE0_ERR
192+
| GPE0_OCISLV_ERR | GPE1_ERR
193+
| GPE1_OCISLV_ERR | GPE2_OCISLV_ERR
194+
| GPE3_OCISLV_ERR | JTAGACC_ERR
195+
| OCB_DB_OCI_RDATA_PARITY | OCB_DB_OCI_SLVERR
196+
| OCB_DB_OCI_TIMEOUT | OCB_DB_PIB_DATA_PARITY_ERR
197+
| OCB_IDC0_ERR | OCB_IDC1_ERR
198+
| OCB_IDC2_ERR | OCB_IDC3_ERR
199+
| OCB_PIB_ADDR_PARITY_ERR | OCC_CMPLX_FAULT
200+
| OCC_CMPLX_NOTIFY | SRAM_CE
201+
| SRAM_DATAOUT_PERR | SRAM_OCI_ADDR_PARITY_ERR
202+
| SRAM_OCI_BE_PARITY_ERR | SRAM_OCI_WDATA_PARITY
203+
| SRAM_READ_ERR | SRAM_SPARE_DIRERR0
204+
| SRAM_SPARE_DIRERR1 | SRAM_SPARE_DIRERR2
205+
| SRAM_SPARE_DIRERR3 | SRAM_UE
206+
| SRAM_WRITE_ERR | SRT_FSM_ERR
207+
| STOP_RCV_NOTIFY_PRD);
208+
write_scom(
209+
iv_proc,
210+
iv_fir_address + MASK_WOR_INCR,
211+
iv_mask | C405ICU_M_TIMEOUT
212+
| CME_ERR_NOTIFY | EXT_TRAP
213+
| FIR_PARITY_ERR_DUP | FIR_PARITY_ERR
214+
| GPE0_HALTED | GPE0_WD_TIMEOUT
215+
| GPE1_HALTED | GPE1_WD_TIMEOUT
216+
| GPE2_ERR | GPE2_HALTED
217+
| GPE2_WD_TIMEOUT | GPE3_ERR
218+
| GPE3_HALTED | GPE3_WD_TIMEOUT
219+
| OCB_ERR | OCC_FW0
220+
| OCC_FW1 | OCC_HB_NOTIFY
221+
| PPC405_CHIP_RESET | PPC405_CORE_RESET
222+
| PPC405_DBGSTOPACK | PPC405_SYS_RESET
223+
| PPC405_WAIT_STATE | SPARE_59
224+
| SPARE_60 | SPARE_61
225+
| SPARE_ERR_38);
226+
write_scom(
227+
iv_proc,
228+
iv_fir_address + MASK_WAND_INCR,
229+
iv_mask & ~C405_ECC_CE
230+
& ~C405_ECC_UE & ~C405_OCI_MC_CHK
231+
& ~C405DCU_M_TIMEOUT & ~GPE0_ERR
232+
& ~GPE0_OCISLV_ERR & ~GPE1_ERR
233+
& ~GPE1_OCISLV_ERR & ~GPE2_OCISLV_ERR
234+
& ~GPE3_OCISLV_ERR & ~JTAGACC_ERR
235+
& ~OCB_DB_OCI_RDATA_PARITY & ~OCB_DB_OCI_SLVERR
236+
& ~OCB_DB_OCI_TIMEOUT & ~OCB_DB_PIB_DATA_PARITY_ERR
237+
& ~OCB_IDC0_ERR & ~OCB_IDC1_ERR
238+
& ~OCB_IDC2_ERR & ~OCB_IDC3_ERR
239+
& ~OCB_PIB_ADDR_PARITY_ERR & ~OCC_CMPLX_FAULT
240+
& ~OCC_CMPLX_NOTIFY & ~SRAM_CE
241+
& ~SRAM_DATAOUT_PERR & ~SRAM_OCI_ADDR_PARITY_ERR
242+
& ~SRAM_OCI_BE_PARITY_ERR & ~SRAM_OCI_WDATA_PARITY
243+
& ~SRAM_READ_ERR & ~SRAM_SPARE_DIRERR0
244+
& ~SRAM_SPARE_DIRERR1 & ~SRAM_SPARE_DIRERR2
245+
& ~SRAM_SPARE_DIRERR3 & ~SRAM_UE
246+
& ~SRAM_WRITE_ERR & ~SRT_FSM_ERR
247+
& ~STOP_RCV_NOTIFY_PRD);
248+
}
249+
250+
static void startOCCFromSRAM(void)
251+
{
252+
// executed only for master processor!!!
253+
if(MASTER_PROC)
254+
{
255+
pm_pss_init();
256+
}
257+
258+
pm_occ_fir_init();
259+
// executed only for master processor!!!
260+
if(MASTER_PROC)
261+
{
262+
clear_occ_special_wakeups();
263+
}
264+
265+
write_scom(PU_OCB_OCI_OIRR0A_SCOM, 0x218780f800000000);
266+
write_scom(PU_OCB_OCI_OIRR1A_SCOM, 0x0003d03c00000000);
267+
write_scom(PU_OCB_OCI_OIRR0B_SCOM, 0x2181801800000000);
268+
write_scom(PU_OCB_OCI_OIRR1B_SCOM, 0x0003d00c00000000);
269+
write_scom(PU_OCB_OCI_OIRR0C_SCOM, 0x010280ac00000000);
270+
write_scom(PU_OCB_OCI_OIRR1C_SCOM, 0x0001901400000000);
271+
272+
// executed only for master processor!!!
273+
if(MASTER_PROC)
274+
{
275+
p9_pm_occ_control(
276+
makeStart405Instruction());
277+
}
278+
279+
write_scom(OCB_OITR0, 0xffffffffffffffff);
280+
write_scom(OCB_OIEPR0, 0xffffffffffffffff);
281+
}
282+
283+
static void p9_pm_occ_control(const uint64_t i_ppc405_jump_to_main_instr)
284+
{
285+
write_scom(PU_SRAM_SRBV3_SCOM, i_ppc405_jump_to_main_instr);
286+
write_scom(PU_JTG_PIB_OJCFG_AND, ~PPC_BIT(JTG_PIB_OJCFG_DBG_HALT_BIT));
287+
write_scom(PU_OCB_PIB_OCR_OR, PPC_BIT(OCB_PIB_OCR_CORE_RESET_BIT));
288+
write_scom(PU_OCB_PIB_OCR_CLEAR, PPC_BIT(OCB_PIB_OCR_CORE_RESET_BIT));
220289
}
221290

222291
static void clear_occ_special_wakeups(void)
@@ -343,75 +412,6 @@ static void p9_pm_ocb_indir_access(
343412
}
344413
}
345414

346-
static void pm_occ_fir_init(void)
347-
{
348-
iv_mask = read_scom(iv_mask_address);
349-
350-
write_scom(iv_proc, iv_fir_address, 0);
351-
write_scom(iv_proc, iv_action0_address, C405_ECC_UE);
352-
write_scom(
353-
iv_proc,
354-
iv_action1_address,
355-
C405_ECC_CE | C405_OCI_MC_CHK
356-
| C405DCU_M_TIMEOUT | GPE0_ERR
357-
| GPE0_OCISLV_ERR | GPE1_ERR
358-
| GPE1_OCISLV_ERR | GPE2_OCISLV_ERR
359-
| GPE3_OCISLV_ERR | JTAGACC_ERR
360-
| OCB_DB_OCI_RDATA_PARITY | OCB_DB_OCI_SLVERR
361-
| OCB_DB_OCI_TIMEOUT | OCB_DB_PIB_DATA_PARITY_ERR
362-
| OCB_IDC0_ERR | OCB_IDC1_ERR
363-
| OCB_IDC2_ERR | OCB_IDC3_ERR
364-
| OCB_PIB_ADDR_PARITY_ERR | OCC_CMPLX_FAULT
365-
| OCC_CMPLX_NOTIFY | SRAM_CE
366-
| SRAM_DATAOUT_PERR | SRAM_OCI_ADDR_PARITY_ERR
367-
| SRAM_OCI_BE_PARITY_ERR | SRAM_OCI_WDATA_PARITY
368-
| SRAM_READ_ERR | SRAM_SPARE_DIRERR0
369-
| SRAM_SPARE_DIRERR1 | SRAM_SPARE_DIRERR2
370-
| SRAM_SPARE_DIRERR3 | SRAM_UE
371-
| SRAM_WRITE_ERR | SRT_FSM_ERR
372-
| STOP_RCV_NOTIFY_PRD);
373-
write_scom(
374-
iv_proc,
375-
iv_fir_address + MASK_WOR_INCR,
376-
iv_mask | C405ICU_M_TIMEOUT
377-
| CME_ERR_NOTIFY | EXT_TRAP
378-
| FIR_PARITY_ERR_DUP | FIR_PARITY_ERR
379-
| GPE0_HALTED | GPE0_WD_TIMEOUT
380-
| GPE1_HALTED | GPE1_WD_TIMEOUT
381-
| GPE2_ERR | GPE2_HALTED
382-
| GPE2_WD_TIMEOUT | GPE3_ERR
383-
| GPE3_HALTED | GPE3_WD_TIMEOUT
384-
| OCB_ERR | OCC_FW0
385-
| OCC_FW1 | OCC_HB_NOTIFY
386-
| PPC405_CHIP_RESET | PPC405_CORE_RESET
387-
| PPC405_DBGSTOPACK | PPC405_SYS_RESET
388-
| PPC405_WAIT_STATE | SPARE_59
389-
| SPARE_60 | SPARE_61
390-
| SPARE_ERR_38);
391-
write_scom(
392-
iv_proc,
393-
iv_fir_address + MASK_WAND_INCR,
394-
iv_mask & ~C405_ECC_CE
395-
& ~C405_ECC_UE & ~C405_OCI_MC_CHK
396-
& ~C405DCU_M_TIMEOUT & ~GPE0_ERR
397-
& ~GPE0_OCISLV_ERR & ~GPE1_ERR
398-
& ~GPE1_OCISLV_ERR & ~GPE2_OCISLV_ERR
399-
& ~GPE3_OCISLV_ERR & ~JTAGACC_ERR
400-
& ~OCB_DB_OCI_RDATA_PARITY & ~OCB_DB_OCI_SLVERR
401-
& ~OCB_DB_OCI_TIMEOUT & ~OCB_DB_PIB_DATA_PARITY_ERR
402-
& ~OCB_IDC0_ERR & ~OCB_IDC1_ERR
403-
& ~OCB_IDC2_ERR & ~OCB_IDC3_ERR
404-
& ~OCB_PIB_ADDR_PARITY_ERR & ~OCC_CMPLX_FAULT
405-
& ~OCC_CMPLX_NOTIFY & ~SRAM_CE
406-
& ~SRAM_DATAOUT_PERR & ~SRAM_OCI_ADDR_PARITY_ERR
407-
& ~SRAM_OCI_BE_PARITY_ERR & ~SRAM_OCI_WDATA_PARITY
408-
& ~SRAM_READ_ERR & ~SRAM_SPARE_DIRERR0
409-
& ~SRAM_SPARE_DIRERR1 & ~SRAM_SPARE_DIRERR2
410-
& ~SRAM_SPARE_DIRERR3 & ~SRAM_UE
411-
& ~SRAM_WRITE_ERR & ~SRT_FSM_ERR
412-
& ~STOP_RCV_NOTIFY_PRD);
413-
}
414-
415415
static void p9_pm_pba_bar_config(
416416
int bar_index,
417417
int bar_address)

0 commit comments

Comments
 (0)