diff --git a/src/include/cpu/power/istep_8.h b/src/include/cpu/power/istep_8.h index 21e1e900b23..f5c340eef57 100644 --- a/src/include/cpu/power/istep_8.h +++ b/src/include/cpu/power/istep_8.h @@ -1,25 +1,111 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef ISTEP_8_H #define ISTEP_8_H +#include #include +typedef enum +{ + AVS_WRITE, + AVS_READ +} avs_operation_t; + +void istep_8_10(void); +void p9_io_xbus_scominit(const uint8_t); +void p9_xbus_g0_scom(void); +void p9_xbus_g1_scom(void); + +void istep_8_9(void); +void p9_fbc_ioe_dl_scom(void); +void p9_fbc_ioe_tl_scom(void); +void p9_fbc_no_hp_scom(void); +void ioe_tl_fir(void); +void ioel_fir(void); + void istep_8_11(void); void istep_8_12(void); +#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) +#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) +#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) + +#define ATTR_PROC_FABRIC_X_LINKS_CNFG (1) + +#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) +#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) + +#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) +#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) + +#define FBC_IOE_DL_FIR_ACTION0 (0) +#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) +#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) + +// Power Bus PB West Mode Configuration Register +#define PB_WEST_MODE_CFG_REG (0x501180A) +// Power Bus PB CENT FIR Register +#define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) +// Power Bus PB CENT Mode Register +#define PB_CENT_MODE_CFG_REG (0x5011C0A) +// Power Bus PB CENT GP command RATE DP0 Register +#define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) +// Power Bus PB CENT GP command RATE DP1 Register +#define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) +// Power Bus PB CENT RGP command RATE DP0 Register +#define PB_CENT_RGP_COMMAND_RATE_DP0_REG (0x5011C28) +// Power Bus PB CENT RGP command RATE DP1 Register +#define PB_CENT_RGP_COMMAND_RATE_DP1_REG (0x5011C29) +// Power Bus PB CENT SP command RATE DP0 Register +#define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) +// Power Bus PB CENT SP command RATE DP1 Register +#define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) +// Power Bus PB East Mode Configuration Register +#define PB_EAST_MODE_CFG_REG (0x501200A) +// Power Bus PBEN IOX Domain FIR0 Mask Register +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) +// Power Bus PBEN IOX Domain FIR Action 0 Register +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) +// Power Bus PBEN IOX Domain FIR Action 1 Register +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +// Power bus Electrical Framer/Parser 01 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) +// Power Bus Electrical Framer/Parser 23 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) +// Power Bus Electrical Framer/Parser 45 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) +// Power Bus Electrical Link Data Buffer 01 Configuration Register +#define PB_ELE_PB_DATA_BUFF_01_CFG_REG (0x5013410) +// Power Bus Electrical Link Data Buffer 23 Configuration Register +#define PB_ELE_PB_DATA_BUFF_23_CFG_REG (0x5013411) +// Power Bus Electrical Link Data Buffer 45 Configuration Register +#define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) +// Power Bus Electrical Miscellaneous Configuration Register +#define PB_ELE_MISC_CFG_REG (0x5013423) +// Power Bus Electrical Link Trace Configuration Register +#define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) +// ELL FIR Mask Register +#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) +// ELL FIR Action 0 Register +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) +// ELL FIR Action 1 Register +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +// Power Bus ELL Configuration Register +#define PB_ELL_CFG_REG (0x601180A) +// Power Bus ELL Replay Threshold Register +#define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) +// Power Bus ELL SL ECC Threshold Register +#define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) +#define XBUS_FIR_MASK_REG (0x6010C03) +#define XBUS_FIR_ACTION0_REG (0x6010C06) +#define XBUS_FIR_ACTION1_REG (0x6010C07) + #define AVS_CRC_DATA_MASK (0xFFFFFFF8) #define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) #define CHIP_EC (0x20) #define SECURE_MEMORY (CHIP_EC >= 0x22) #define ID_OFFSET (32) -typedef enum -{ - AVS_WRITE, - AVS_READ -} avs_operation_t; - #define PU_NPU_SM2_XTS_ATRMISS_ENA PPC_BIT(63) #define ATTR_LINK_TRAIN_BOTH (0) diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index 869b143b659..39aee686341 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -7,6 +7,8 @@ bootblock-y += rom_media.c romstage-y += rom_media.c romstage-y += romstage.c romstage-y += vpd.c +romstage-y += istep_8_9.c +romstage-y += istep_8_10.c romstage-y += istep_8_11.c romstage-y += istep_8_12.c romstage-y += istep_13_2.c diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c new file mode 100644 index 00000000000..d0ad233c655 --- /dev/null +++ b/src/soc/ibm/power9/istep_8_10.c @@ -0,0 +1,1220 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void istep_8_10(void) +{ + printk(BIOS_EMERG, "starting istep 8.10\n"); + report_istep(8, 10); + printk(BIOS_EMERG, "starting p9_io_xbus_scominit(0);\n"); + p9_io_xbus_scominit(0); + printk(BIOS_EMERG, "ending p9_io_xbus_scominit(0);\n"); + printk(BIOS_EMERG, "starting p9_io_xbus_scominit(1);\n"); + p9_io_xbus_scominit(1); + printk(BIOS_EMERG, "ending p9_io_xbus_scominit(1);\n"); + printk(BIOS_EMERG, "ending istep 8.10\n"); + return; +} + +void p9_io_xbus_scominit(const uint8_t group) +{ + printk(BIOS_EMERG, "starting 1 0x8009F8000000003F\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009F8000000003F, PPC_BIT(52)); + printk(BIOS_EMERG, "ending 1 0x8009F8000000003F\n"); + wait_us(50, false); + printk(BIOS_EMERG, "starting 2 0x800C9C000000003F\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800C9C000000003F, PPC_BIT(48)); + printk(BIOS_EMERG, "ending 2 0x800C9C000000003F\n"); + wait_us(50, false); + printk(BIOS_EMERG, "starting 3 0x800c14000000003f\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800c14000000003f, 0x20); + printk(BIOS_EMERG, "ending 3 0x800c14000000003f\n"); + if(0 == group) + { + p9_xbus_g0_scom(); + } + else if(1 == group) + { + p9_xbus_g1_scom(); + } + + if(!(read_scom(PB_CENT_SM0_PB_CENT_FIR_REG) & PPC_BIT(13))) + { + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); + } +} + +void p9_xbus_g0_scom() +{ + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000000006010C3F | id << 32, + ~PPC_BITMASK(53, 55)); + } + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000080006010C3F | id << 32, + ~PPC_BIT(54)); + } + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, PPC_BIT(54)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000080006010C3F | 0x11ull << 32, + PPC_BIT(54)); + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000280006010C3F | id << 32, + ~PPC_BITMASK(44, 56)); + } + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL + scom_and_or_for_chiplet(XB_CHIPLET_ID, + 0x8000300006010C3F | id << 32, + ~PPC_BITMASK(52, 60), + PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + } + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000C00006010C3F | id << 32, + ~PPC_BITMASK(48, 60)); + } + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + scom_and_for_chiplet(XB_CHIPLET_ID, + 0x8002200006010C3F | id << 32, + ~PPC_BIT(48)); + } + + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00106010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00206010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00306010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00406010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00506010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00606010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00706010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00806010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00906010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00A06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00B06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00C06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00D06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00E06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00F06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C01006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); + + + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80106010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80206010C3F, + ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80306010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80406010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80506010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80606010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80706010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80806010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80906010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80A06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80B06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80C06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80D06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80E06010C3F, + ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80F06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C81006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); + + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8004040006010C3F | id << 32, + ~PPC_BIT(48)); + } + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x80040C0006010C3F | id << 32, + PPC_BIT(62)); + } + + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0006010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0106010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0206010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0306010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0406010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0506010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0606010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0706010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0806010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0906010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0A06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0B06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0C06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0D06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0E06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0F06010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C1006010C3F, + ~PPC_BITMASK(48, 63)); + + + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440106010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440206010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440306010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440406010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440506010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(50)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440606010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440706010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440806010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440906010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440A06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440B06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440C06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440D06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440E06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440F06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004441006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); + + + // register P9A_XBUS_0_RX0_RX_SPARE_MODE_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008000006010C3F, + PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RX_ID1_PG + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8008080006010C3F, + ~PPC_BITMASK(48, 53)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE1_EO_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8008100006010C3F, + ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE5_EO_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008300006010C3F, + ~PPC_BITMASK(51, 55), + PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE7_EO_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008400006010C3F, + ~PPC_BITMASK(60, 63), + PPC_BIT(62) | PPC_BIT(60)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008C00006010C3F, + ~PPC_BITMASK(55, 60), + PPC_BIT(51) | PPC_BITMASK(56, 60)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008D00006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009700006010C3F, + PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009800006010C3F, + ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), + PPC_BIT(59)); + // P9A_XBUS_0_RX1_RX_ID2_PG + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009900006010C3F, + PPC_BITMASK(57, 58)); + // P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009980006010C3F, + ~PPC_BITMASK(48, 52), + PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009A00006010C3F, + ~PPC_BITMASK(48, 51), + PPC_BIT(48) | PPC_BITMASK(50, 51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009B00006010C3F, + ~PPC_BITMASK(48, 51), + PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009B80006010C3F, + ~PPC_BITMASK(44, 56), + PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009C80006010C3F, + ~(PPC_BITMASK(48, 58) | PPC_BITMASK(61, 63)), + PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009D00006010C3F, + ~PPC_BITMASK(48, 58), + PPC_BITMASK(50, 56) | PPC_BIT(58)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8009E00006010C3F, + ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009E80006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x800A800006010C3F, + PPC_BIT(11) | PPC_BIT(35)); + // register P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800AE80006010C3F, + ~PPC_BITMASK(56, 57), + PPC_BIT(58)); + // register P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800AF80006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + // register P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800B800006010C3F, + ~PPC_BIT(60)); + // register P9A_XBUS_0_TX1_TX_SPARE_MODE_PG + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C040006010C3F, + ~PPC_BITMASK(56, 57)); + // register P9A_XBUS_0_TX1_TX_ID1_PG + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C0C0006010C3F, + ~PPC_BITMASK(48, 53)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C140006010C3F, + ~(PPC_BITMASK(53, 57) | PPC_BIT(48)), + PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C1C0006010C3F, + ~PPC_BITMASK(56, 62), + PPC_BIT(58) | PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C240006010C3F, + ~PPC_BITMASK(48, 49)); + // register P9A_XBUS_0_TX1_TX_ID2_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C840006010C3F, + ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), + PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C8C0006010C3F, + ~PPC_BITMASK(55, 59), + PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800CEC0006010C3F, + ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800CF40006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x800D2C0006010C3F, + PPC_BIT(59)); + // register P9A_XBUS_0_TX_IMPCAL_P_4X_PB + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800F1C0006010C3F, + ~PPC_BITMASK(48, 52), + PPC_BITMASK(49, 51)); +} + +void p9_xbus_g1_scom() +{ + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000002006010C3F | id << 32, + ~PPC_BITMASK(53, 55)); + } + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000082006010C3F | id << 32, + ~PPC_BIT(54)); + } + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8000083106010C3F | 0x11ull << 32, + PPC_BIT(54)); + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000282006010C3F | id << 32, + ~PPC_BITMASK(44, 56)); + } + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8000302006010C3F | id << 32, + ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + } + + for(uint64_t id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000C02006010C3F | id << 32, + ~PPC_BITMASK(48, 60)); + } + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002202006010C3F | id << 32, + ~PPC_BIT(48)); + } + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F | 0x11ull << 32, PPC_BIT(48)); + + + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + + + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82206010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82E06010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8004042006010C3F | id << 32, + ~PPC_BIT(48)); + } + + for(uint64_t id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x80040C2006010C3F | id << 32, + PPC_BIT(62)); + } + + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2106010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2806010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2F06010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, ~PPC_BITMASK(48, 63)); + + + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442206010C3F, ~(PPC_BITMASK(48, 51) | PPC_BITMASK(56, 63)), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(42)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + + + // register P9A_XBUS_0_RX1_RX_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RX_ID1_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008082006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE1_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008102006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008302006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE7_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008402006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(48, 49), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C02006010C3F, ~PPC_BIT(55), PPC_BITMASK(56, 60)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009702006010C3F, PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_ID2_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009802006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009902006010C3F, PPC_BITMASK(57, 58)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009982006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B82006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C82006010C3F, PPC_BITMASK(48, 55) | PPC_BITMASK(61, 63), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D02006010C3F, ~PPC_BITMASK(53, 63), PPC_BITMASK(54, 59) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE11_E_PG + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E02006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A802006010C3F, PPC_BIT(50) | PPC_BIT(56)); + // register P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE82006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(56)); + // register P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + // register P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B802006010C3F, ~PPC_BIT(60)); + // register P9A_XBUS_0_TX1_TX_SPARE_MODE_PG + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C042006010C3F, ~PPC_BITMASK(56, 57)); + // register P9A_XBUS_0_TX1_TX_ID1_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C0C2006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C142006010C3F, ~(PPC_BIT(48) | PPC_BITMASK(53, 57)), PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C2006010C3F, ~PPC_BITMASK(56, 62), PPC_BITMASK(52, 55) | PPC_BIT(58) | PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C242006010C3F, ~PPC_BITMASK(48, 49)); + // register P9A_XBUS_0_TX1_TX_ID2_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C842006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C2006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC2006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF42006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C2006010C3F, PPC_BIT(59)); + // register P9A_XBUS_0_TX_IMPCAL_P_4X_PB + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); +} diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c new file mode 100644 index 00000000000..e9877314462 --- /dev/null +++ b/src/soc/ibm/power9/istep_8_9.c @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void istep_8_9(void) +{ + printk(BIOS_EMERG, "starting istep 8.9\n"); + printk(BIOS_EMERG, "starting istep 8.9\n"); + printk(BIOS_EMERG, "starting istep 8.9\n"); + report_istep(8, 9); + p9_fbc_no_hp_scom(); + p9_fbc_ioe_tl_scom(); + ioe_tl_fir(); + p9_fbc_ioe_dl_scom(); + ioel_fir(); + printk(BIOS_EMERG, "ending istep 8.9\n"); +} + +void p9_fbc_ioe_dl_scom(void) +{ + // PB_ELL_CFG_REG + // [0] CONFIG_LINK_PAIR: When 1, the two links operate as a pair. + // When 0, only one link is used or they are independent. + // [2] CONFIG_CRC_LANE_ID: When 1, use lane IDs from CRC for lane sparing. + // [4] CONFIG_SL_UE_CRC_ERR: When 1, UEs on the SL ECC cause the packet + // to be treated as a CRC error. + // [8:11] CONFIG_UNUSED1: Spare bits. + // [12:15] CONFIG_PACKET_DELAY_LIMIT: This field indicates the number + // of cycles of delay of frame data that are required for the + // packet to be considered delayed or replayed. (0 is 16 cycles.) + // [28:31] CONFIG_AUTO_TDM_ERROR_RATE: This field contains the error rate + // for the auto-entry TDM mode. + printk(BIOS_EMERG, "1 starting\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, PPC_BIT(0) | PPC_BIT(2) | PPC_BIT(4) | PPC_BITMASK(12, 15) | PPC_BITMASK(28, 31)); + printk(BIOS_EMERG, "1 ending\n"); + // PB_ELL_REPLAY_TRESHOLD_REG + // [0:3] THRESH_REPLAY_TB_SEL: Replay threshold timebase select. + // [4:7] THRESH_REPLAY_TAP_SEL: Replay threshold tap select. + // [8:10] THRESH_REPLAY_ENABLE: Replay threshold error enable. + printk(BIOS_EMERG, "2 starting\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, PPC_BITMASK(1, 2) | PPC_BITMASK(4, 10)); + printk(BIOS_EMERG, "2 ending\n"); + // PB_ELL_SL_ECC_TRESHOLD_REG + // [0:3] THRESH_SL_ECC_TB_SEL: SL ECC threshold timebase select. + // [4:7] THRESH_SL_ECC_TAP_SEL: SL ECC threshold tap select. + // [8:9] THRESH_SL_ECC_ENABLE: SL ECC threshold error enable. + // [10:25] THRESH_SL_ECC_UNUSED1: Spare bits. + printk(BIOS_EMERG, "3 starting\n"); + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, PPC_BITMASK(1, 10)); + printk(BIOS_EMERG, "3 ending\n"); +} + +void ioe_tl_fir(void) +{ + // PB_IOE_FIR_ACTION0: Processor bus IOE domain action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) Checkstop. + // (0,1) Recoverable Error to Service Processor. + // (1,0) Special Attention to Service Processor. + // (1,1) Invalid. + write_scom(PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + // PB_IOE_FIR_ACTION1: Processor bus FIR LSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) Checkstop. + // (0,1) Recoverable Error to Service Processor. + // (1,0) Special Attention to Service Processor. + // (1,1) Invalid. + write_scom(PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + // PU_PB_IOE_FIR_MASK_REG: Power Bus PBEN IOX Domain FIR0 Mask Register + // [0:5] FMR[0:5]_TRAINED_MASK fmr[0:5] trained. + // [6:7] RSV[6:7]_MASK rsv[6:7] mask. + // [8] DOB01_UE_MASK: dob01 ue mask. + // [9] DOB01_CE_MASK: dob01 ce mask. + // [10] DOB01_SUE_MASK: dob01 sue mask. + // [11] DOB23_UE_MASK: dob23 ue mask. + // [12] DOB23_CE_MASK: dob23 ce mask. + // [13] DOB23_SUE_MASK: dob23 sue mask. + // [14] DOB45_UE_MASK: dob45 ue mask. + // [15] DOB45_CE_MASK: dob45 ce mask. + // [16] DOB45_SUE_MASK: dob45 sue mask. + // [17:19] RSV17_MASK: rsv[17:19] mask. + // [20:25] FRAMER[0:5]_ATTN_MASK: framer[0:5] attn mask. + // [26:27] RSV[26:27]_MASK: rsv[26:27] mask. + // [28:33] PARSER[0:5]_ATTN_MASK: parser[0:5] attn mask. + // [34:35] RSV[34:35]_MASK: rsv[34:35] mask. + // [36:37] MB[0:1]_SPATTN_MASK: mb[0:1] spattn mask. + // [38:39] MB[10:11]_SPATTN_MASK: mb[10:11] spattn mask. + // [40:41] MB[20:21]_SPATTN_MASK: mb[20:21] spattn mask. + // [42:43] MB[30:31]_SPATTN_MASK: mb[30:31] spattn mask. + // [44:45] MB[40:41]_SPATTN_MASK: mb[40:41] spattn mask. + // [46:47] MB[50:51]_SPATTN_MASK: mb[50:51] spattn mask. + // [48:51] Reserved. + // [52] DOB01_ERR_MASK: data outbound switch internal error mask - links 01. + // [53] DOB23_ERR_MASK: data outbound switch internal error mask - links 23. + // [54] DOB45_ERR_MASK: data outbound switch internal error mask - links 45. + // [55] Reserved. + // [56] DIB01_ERR_MASK: data inbound switch internal error mask - links 01. + // [57] DIB23_ERR_MASK: data inbound switch internal error mask - links 23. + // [58] DIB45_ERR_MASK: data inbound switch internal error mask - links 45. + // [59:61] Reserved. + // [62] FIR_SCOM_ERR_MASK_DUP: FIR SCOM err mask dup. + // [63] FIR_SCOM_ERR_MASK: FIR SCOM err mask. + write_scom(PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK | FBC_IOE_TL_FIR_MASK_X0_NF); +} + +void ioel_fir(void) +{ + // IOEL_FIR_ACTION0: processor bus FIR MSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) = Checkstop. + // (0,1) = Recoverable error to service processor. + // (1,0) = Special attention to service processor. + // (1,1) = Invalid. + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + // IOEL_FIR_ACTION1: processor bus FIR LSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) = Checkstop. + // (0,1) = Recoverable error to service processor. + // (1,0) = Special attention to service processor. + // (1,1) = Invalid. + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + // XBUS_LL0_IOEL_FIR_MASK_REG: This register provides a bit mask for the ELL FIR Register. + // [0:1] FIR_LINK[0:1]_TRAINED_MASK: Link [0:1] trained mask. + // [2:3] RESERVED. + // [4:5] FIR_LINK[0:1]_REPLAY_THRESHOLD_MASK: Link [0:1] replay threshold mask. + // [6:7] FIR_LINK[0:1]_CRC_ERROR_MASK: Link [0:1] CRC error mask. + // [8:9] FIR_LINK[0:1]_NAK_RECEIVED_MASK: Link [0:1] NAK received mask. + // [10:11] FIR_LINK[0:1]_REPLAY_BUFFER_FULL_MASK: Link [0:1] replay buffer full mask. + // [12:13] FIR_LINK[0:1]_SL_ECC_THRESHOLD_MASK: Link [0:1] SL ECC threshold mask. + // [14:15] FIR_LINK[0:1]_SL_ECC_CORRECTABLE_MASK: Link [0:1] SL ECC correctable mask. + // [16:17] FIR_LINK[0:1]_SL_ECC_UE_MASK: Link [0:1] SL ECC UE mask. + // [18:39] RESERVED. + // [40:41] FIR_LINK[0:1]_TCOMPLETE_BAD_MASK: Link [0:1] complete bad mask. + // [42:43] RESERVED. + // [44:45] FIR_LINK[0:1]_SPARE_DONE_MASK: Link [0:1] spare done mask. + // [46:47] FIR_LINK[0:1]_TOO_MANY_CRC_ERRORS_MASK: Link [0:1] too many CRC errors mask. + // [48:50] RESERVED. + // [51] FIR_PSAVE_INVALID_STATE_MASK: Psave invalid state mask. + // [52:53] FIR_LINK[0:1]_CORRECTABLE_ARRAY_ERROR_MASK: Link [0:1] correctable array error mask. + // [54:55] FIR_LINK[0:1]_UNCORRECTABLE_ARRAY_ERROR_MASK: Link [0:1] uncorrectable array error mask. + // [56:57] FIR_LINK[0:1]_TRAINING_FAILED_MASK: Link [0:1] training failed mask. + // [58:59] FIR_LINK[0:1]_UNRECOVERABLE_ERROR_MASK: Link [0:1] unrecoverable error mask. + // [60:61] FIR_LINK[0:1]_INTERNAL_ERROR_MASK: Link [0:1] internal error mask. + // [62] FIR_SCOM_ERR_DUP_MASK: FIR SCOM error dup mask. + // [63] FIR_SCOM_ERR_MASK: FIR SCOM error mask. + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); +} + +void p9_fbc_no_hp_scom(void) +{ + // PB_WEST_MODE_CFG_REG: Power Bus west mode configuration register + // [16:22] PB_CFG_SP_HW_MARK: configures the maximum system pumps an IO unit may issue. + // [23:29] PB_CFG_GP_HW_MARK: configures the maximum group pumps this chip may issue. + // [30:35] PB_CFG_LCL_HW_MARK: configures the maximum local pumps this chip may issue. + scom_and_or(PB_WEST_MODE_CFG_REG, ~PPC_BITMASK(16, 35), 0xFAFEA0000000); + // PB_CENT_MODE_CFG_REG: Power Bus PB CENT Mode Register + // [16:22] PB_CFG_SP_HW_MARK: Configures the maximum system pumps an IO unit may issue. + // [23:29] PB_CFG_GP_HW_MARK: Configures the maximum group pumps this chip may issue. + // [30:35] PB_CFG_LCL_HW_MARK: Configures the maximum local pumps this chip may issue. + scom_and_or(PB_CENT_MODE_CFG_REG, ~PPC_BITMASK(16, 35), 0x7EFEA0000000); + // PB_CENT_GP_COMMAND_RATE_DP0_REG: Power Bus PB CENT GP command RATE DP0 Register + // PB_CFG_GP_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for group pump drop priority 0 at level [0:7]. + write_scom(PB_CENT_GP_COMMAND_RATE_DP0_REG, 0); + // PB_CENT_GP_COMMAND_RATE_DP1_REG: Power Bus PB CENT GP command RATE DP1 Register + // PB_CFG_GP_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for group pump drop priority 1 at level [0:7]. + write_scom(PB_CENT_GP_COMMAND_RATE_DP1_REG, 0); + // PB_CENT_RGP_COMMAND_RATE_DP0_REG: Power Bus PB CENT RGP command RATE DP0 Register + // RWX PB_CFG_RNS_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for remote group pump drop priority 0 at level [0:7]. + write_scom(PB_CENT_RGP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + // PB_CENT_RGP_COMMAND_RATE_DP1_REG: Power Bus PB CENT RGP command RATE DP1 Register + // PB_CFG_RNS_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for remote group pump drop priority 1 at level [0:7]. + write_scom(PB_CENT_RGP_COMMAND_RATE_DP1_REG, 0x40508080A0C1218); + // PB_CENT_SP_COMMAND_RATE_DP0_REG: Power Bus PB CENT SP command RATE DP0 Register + // PB_CFG_VG_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for system pump drop priority 0 at level [0:7]. + write_scom(PB_CENT_SP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + // PB_CENT_SP_COMMAND_RATE_DP1_REG: Power Bus PB CENT SP command RATE DP1 Register + // PB_CFG_VG_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for system pump drop priority 1 at level [0:7]. + write_scom(PB_CENT_SP_COMMAND_RATE_DP1_REG, 0x30406080A0C1218); + // PB_EAST_MODE_CFG_REG: Power Bus PB East Mode Configuration Register + // [0] pb_east_pbixxx_init + // [1:3] spare + // [4] PB_CFG_CHIP_IS_SYSTEM: configures whether there are other POWER9s in the system. + // [5:7] spare + // [8] PB_CFG_HNG_CHK_DISABLE: Hang Check Disable. + // [9] PB_DBG_CLR_MAX_HANG_STAGE: Resets the maximum hang state level (pb_hang_level). + // [10:11] spare 12:15 pb_cfg_east_sw_ab_wait(0:3) + // [12:15] PB_CFG_SW_AB_WAIT: Adds delay to tc_pb_switch_ab input from TPC during hot plug sequence. + scom_and_or(PB_EAST_MODE_CFG_REG, 0xF1FF00000FFFFFFF, 0x7EFE0000000); +} + +void p9_fbc_ioe_tl_scom(void) +{ + // PB_ELE_PB_FRAMER_PARSER_01_CFG_REG Power Bus Electrical Framer/Parser 01 Configuration Register + // [0] FP0_CREDIT_PRIORITY_4_NOT_8: fp0 credit priority 4 not 8. + // [1] FP0_DISABLE_GATHERING: fp0 disable data gathering. + // [2] FP0_DISABLE_CMD_COMPRESSION: fp0 disable command compression. + // [3] FP0_DISABLE_PRSP_COMPRESSION: fp0 disable prsp compression. + // [4:11] FP0_LL_CREDIT_LO_LIMIT: fp0 ll credit low limit - normal frames in flight limit. Set to ROUNDUP(25.5 - (nest freq/elec freq)*10.75)). + // [12:19] FP0_LL_CREDIT_HI_LIMIT: fp0 ll credit high limit - frames in flight limit during stop_cmds/replay. + // [20] FP0_FMR_DISABLE: fp0 framer disable - turn the framer clocks OFF. + // [21] FP0_FMR_SPARE: fp0 framer spare. + // [22:23] FP01_CMD_EXP_TIME: obs/fmr/prs command expiration time = (value * 2) + 9. + // [24] FP0_RUN_AFTER_FRAME_ERROR: fp0 run after frame error. + // [25] FP0_PRS_DISABLE: fp0 parser disable - turn the parser clocks OFF. + // [26:31] FP0_PRS_SPARE: fp0 parser spare. + // [32] FP1_CREDIT_PRIORITY_4_NOT_8: fp1 credit priority 4 not 8. + // [33] FP1_DISABLE_GATHERING: fp1 disable data gathering. + // [34] FP1_DISABLE_CMD_COMPRESSION: fp1 disable command compression. + // [35] FP1_DISABLE_PRSP_COMPRESSION: fp1 disable prsp compression. + // [36:43] FP1_LL_CREDIT_LO_LIMIT: fp1 ll credit low limit - normal frames in flight limit. Set to ROUNDUP(25.5 - (nest freq/elec freq)*10.75)). + // [44:51] FP1_LL_CREDIT_HI_LIMIT: fp1 ll credit high limit - frames in flight limit during stop_cmds/replay. + // [52] FP1_FMR_DISABLE: fp1 framer disable - turn the framer clocks OFF. + // [53:55] FP1_FMR_SPARE: fp1 framer spare. + // [56] FP1_RUN_AFTER_FRAME_ERROR: fp1 run after frame error. + // [57] FP1_PRS_DISABLE: fp1 parser disable - turn the parser clocks OFF. + // [58:63] FP1_PRS_SPARE: fp1 parser spare. + scom_and_or(PB_ELE_PB_FRAMER_PARSER_01_CFG_REG, 0xfff004fffff007bf, 0x2010000020000); + // PB_ELE_PB_DATA_BUFF_01_CFG_REG: Power Bus Electrical Link Data Buffer 01 Configuration Register + // [0] Reserved. + // [1:7] PB_CFG_LINK0_DOB_LIMIT: pb configuration link0 dob limit - total link credits avail. + // [8] Reserved. + // [9:15] PB_CFG_LINK0_DOB_VC0_LIMIT: pb configuration link0 dob vc0 limit - vc0 link credits max. + // [16] Reserved. + // [17:23] PB_CFG_LINK0_DOB_VC1_LIMIT: pb configuration link0 dob vc1 limit - vc1 link credits max. + // [24:28] PB_CFG_LINK01_DIB_VC_LIMIT: pb configuration link01 dib vc limit - limit per VC for data inbound to + // pbien/s (set to 31/16/8 for 1/2/4 channels in use) (both links use same credit pool). + // [29:32] Reserved. + // [33:39] PB_CFG_LINK1_DOB_LIMIT: pb configuration link1 dob limit - total link credits avail. + // [40] Reserved. + // [41:47] PB_CFG_LINK1_DOB_VC0_LIMIT: pb configuration link1 dob vc0 limit - vc0 link credits max. + // [48] Reserved. + // [49:55] PB_CFG_LINK1_DOB_VC1_LIMIT: pb configuration link1 dob vc1 limit - vc1 link credits max. + scom_and_or(PB_ELE_PB_DATA_BUFF_01_CFG_REG, 0x808080FF808080FF, 0x403C3C1F403C3C00); + // PB_ELE_LINK_TRACE_CFG_REG:Power Bus Electrical Link Trace Configuration Register + // [0:3] LINK00_HI_TRACE_CFG: link00 high trace configuration. + // [4:7] LINK00_LO_TRACE_CFG: link00 low trace configuration. + // [8:11] LINK01_HI_TRACE_CFG: link01 high trace configuration. + // [12:15] LINK01_LO_TRACE_CFG: link01 low trace configuration. + scom_and_or(PB_ELE_LINK_TRACE_CFG_REG, 0x00FFFFFFFFFFFF, 0x4141000000000000); + // PB_ELE_PB_FRAMER_PARSER_23_CFG_REG: Power Bus Electrical Framer/Parser 23 Configuration Register + // [20] FP2_FMR_DISABLE: fp2 framer disable - turn the framer clocks OFF. + // [25] FP2_PRS_DISABLE: fp2 parser disable - turn the parser clocks OFF. + // [52] FP3_FMR_DISABLE: fp3 framer disable - turn the framer clocks OFF. + // [57] FP3_PRS_DISABLE: fp3 parser disable - turn the parser clocks OFF. + scom_or(PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, PPC_BIT(20) | PPC_BIT(25) | PPC_BIT(52) | PPC_BIT(57)); + // PB_ELE_PB_FRAMER_PARSER_45_CFG_REG Power Bus Electrical Framer/Parser 45 Configuration Register + // [20] FP4_FMR_DISABLE: fp4 framer disable - turn the framer clocks OFF. + // [25] FP4_PRS_DISABLE: fp4 parser disable - turn the parser clocks OFF. + // [52] FP5_FMR_DISABLE: fp5 framer disable - turn the framer clocks OFF. + // [57] FP5_PRS_DISABLE: fp5 parser disable - turn the parser clocks OFF. + scom_or(PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, PPC_BIT(20) | PPC_BIT(25) | PPC_BIT(52) | PPC_BIT(57)); + // PB_ELE_MISC_CFG_REG: Power Bus Electrical Miscellaneous Configuration Register + // [0] PB_CFG_IOE01_IS_LOGICAL_PAIR: pb configuration ioe01 is logical pair. + // [1] PB_CFG_IOE23_IS_LOGICAL_PAIR: pb configuration ioe23 is logical pair. + // [2] PB_CFG_IOE45_IS_LOGICAL_PAIR: pb configuration ioe45 is logical pair. + scom_and_or(PB_ELE_MISC_CFG_REG, ~PPC_BITMASK(1, 2), PPC_BIT(0)); +} diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index d94a7a2f0d0..cae0b43bfad 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -344,6 +344,8 @@ void main(void) vpd_pnor_main(); prepare_dimm_data(); + // istep_8_9(); + istep_8_10(); istep_8_11(); istep_8_12(); report_istep(13,1); // no-op