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danngreendanngreen
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Remove debugging from mp13x clock init. Allow MPU_MHz to be set by board conf
1 parent cbb07f6 commit 8ffcfb0

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+3
-142
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1 file changed

+3
-142
lines changed

‎src/mp13x/drivers/clocks.hh‎

Lines changed: 3 additions & 142 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,4 @@
11
#pragma once
2-
#include "drivers/leds.hh"
3-
42
#include "drivers/rcc.hh"
53
#include "stm32mp13xx_hal_rcc.h"
64

@@ -14,20 +12,12 @@ struct SystemClocks {
1412

1513
HAL_Init();
1614

17-
Led<GPIO::B, PinNum::_3, LedActive::High> d;
18-
Led<GPIO::B, PinNum::_4, LedActive::High> e;
19-
e.on();
20-
d.off();
21-
d.on();
22-
d.off();
23-
e.off();
24-
2515
constexpr uint32_t pll1m = 2;
26-
const uint32_t pll1n = 54; //(MPU_MHz == 650 ? 81U : 100U);
2716
constexpr uint32_t pll1p = 1;
2817
constexpr uint32_t pll1q = 2;
2918
constexpr uint32_t pll1r = 2;
3019
constexpr uint32_t pll1frac = 0;
20+
const uint32_t pll1n = MPU_MHz / ((HSE_Clock / 1000000) / (pll1m * pll1p));
3121

3222
constexpr uint32_t pll2m = 2;
3323
constexpr uint32_t pll2n = 44;
@@ -46,8 +36,7 @@ struct SystemClocks {
4636
// Turn HSE off
4737
OscEnableHSEON::clear();
4838
while (HSEClockReady::read()) {
49-
d.on();
50-
d.off();
39+
;
5140
}
5241

5342
// Select the source
@@ -70,15 +59,10 @@ struct SystemClocks {
7059

7160
OscEnableHSEON::set();
7261
while (!HSEClockReady::read()) {
73-
d.on();
74-
d.on();
75-
d.off();
62+
;
7663
}
7764
}
7865

79-
e.on();
80-
e.off();
81-
8266
// PLL1
8367
{
8468
PLL1::DIVPEnable::clear();
@@ -109,11 +93,6 @@ struct SystemClocks {
10993
PLL1::DIVREnable::set();
11094
}
11195

112-
e.on();
113-
e.off();
114-
e.on();
115-
e.off();
116-
11796
// PLL2
11897
{
11998
PLL2::DIVPEnable::clear();
@@ -142,17 +121,6 @@ struct SystemClocks {
142121
PLL2::DIVREnable::set();
143122
}
144123

145-
e.on();
146-
e.on();
147-
e.off();
148-
e.off();
149-
e.on();
150-
e.off();
151-
e.on();
152-
e.on();
153-
e.off();
154-
e.off();
155-
156124
MPUClockSrc::write(MPUClockSrcPLL1);
157125
while (!MPUClockSrcReady::read())
158126
;
@@ -165,115 +133,8 @@ struct SystemClocks {
165133
while (!AXIDivReady::read())
166134
;
167135

168-
e.on();
169-
e.off();
170-
e.on();
171-
e.off();
172-
173136
float coreclock = (float)HSE_Clock * ((float)pll1n + (float)pll1frac / 8191.f) / ((float)pll1m * (float)pll1p);
174137
SystemCoreClock = static_cast<uint32_t>(coreclock);
175138
return SystemCoreClock;
176-
177-
// HAL_RCC_DeInit();
178-
179-
// RCC_ClkInitTypeDef RCC_ClkInitStructure;
180-
// RCC_OscInitTypeDef RCC_OscInitStructure;
181-
182-
// /* Enable all available oscillators*/
183-
// RCC_OscInitStructure.OscillatorType =
184-
// (RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_LSI |
185-
// RCC_OSCILLATORTYPE_LSE);
186-
187-
// RCC_OscInitStructure.HSIState = RCC_HSI_ON;
188-
// RCC_OscInitStructure.HSEState = RCC_HSE_ON;
189-
// RCC_OscInitStructure.LSEState = RCC_LSE_ON;
190-
// RCC_OscInitStructure.LSIState = RCC_LSI_ON;
191-
// RCC_OscInitStructure.CSIState = RCC_CSI_ON;
192-
193-
// RCC_OscInitStructure.HSICalibrationValue = 0x00; // Default reset value
194-
// RCC_OscInitStructure.CSICalibrationValue = 0x10; // Default reset value
195-
// RCC_OscInitStructure.HSIDivValue = RCC_HSI_DIV1; // Default value
196-
197-
// /* PLL configuration */
198-
// RCC_OscInitStructure.PLL.PLLState = RCC_PLL_ON;
199-
// RCC_OscInitStructure.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
200-
// RCC_OscInitStructure.PLL.PLLM = 3;
201-
// RCC_OscInitStructure.PLL.PLLN = 81;
202-
// RCC_OscInitStructure.PLL.PLLP = 1;
203-
// RCC_OscInitStructure.PLL.PLLQ = 2;
204-
// RCC_OscInitStructure.PLL.PLLR = 2;
205-
// RCC_OscInitStructure.PLL.PLLFRACV = 0x800;
206-
// RCC_OscInitStructure.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
207-
208-
// RCC_OscInitStructure.PLL2.PLLState = RCC_PLL_ON;
209-
// RCC_OscInitStructure.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
210-
// RCC_OscInitStructure.PLL2.PLLM = 3;
211-
// RCC_OscInitStructure.PLL2.PLLN = 66;
212-
// RCC_OscInitStructure.PLL2.PLLP = 2;
213-
// RCC_OscInitStructure.PLL2.PLLQ = 2;
214-
// RCC_OscInitStructure.PLL2.PLLR = 1;
215-
// RCC_OscInitStructure.PLL2.PLLFRACV = 0x1400;
216-
// RCC_OscInitStructure.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
217-
218-
// RCC_OscInitStructure.PLL3.PLLState = RCC_PLL_ON;
219-
// RCC_OscInitStructure.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
220-
// RCC_OscInitStructure.PLL3.PLLM = 2;
221-
// RCC_OscInitStructure.PLL3.PLLN = 34;
222-
// RCC_OscInitStructure.PLL3.PLLP = 2;
223-
// RCC_OscInitStructure.PLL3.PLLQ = 17;
224-
// RCC_OscInitStructure.PLL3.PLLR = 2;
225-
// RCC_OscInitStructure.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
226-
// RCC_OscInitStructure.PLL3.PLLFRACV = 0x1a04;
227-
// RCC_OscInitStructure.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
228-
229-
// RCC_OscInitStructure.PLL4.PLLState = RCC_PLL_ON;
230-
// RCC_OscInitStructure.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
231-
// RCC_OscInitStructure.PLL4.PLLM = 2;
232-
// RCC_OscInitStructure.PLL4.PLLN = 50;
233-
// RCC_OscInitStructure.PLL4.PLLP = 12;
234-
// RCC_OscInitStructure.PLL4.PLLQ = 60;
235-
// RCC_OscInitStructure.PLL4.PLLR = 6;
236-
// RCC_OscInitStructure.PLL4.PLLRGE = RCC_PLL4IFRANGE_1;
237-
// RCC_OscInitStructure.PLL4.PLLFRACV = 0;
238-
// RCC_OscInitStructure.PLL4.PLLMODE = RCC_PLL_INTEGER;
239-
240-
// /* Enable access to RTC and backup registers */
241-
// SET_BIT(PWR->CR1, PWR_CR1_DBP);
242-
// /* Configure LSEDRIVE value */
243-
// __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
244-
245-
// if (HAL_RCC_OscConfig(&RCC_OscInitStructure) != HAL_OK) {
246-
// return 0;
247-
// }
248-
249-
// /* Select PLLx as MPU, AXI and MCU clock sources */
250-
// RCC_ClkInitStructure.ClockType =
251-
// (RCC_CLOCKTYPE_MPU | RCC_CLOCKTYPE_ACLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5 |
252-
// RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK6 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3);
253-
254-
// RCC_ClkInitStructure.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
255-
// RCC_ClkInitStructure.MPUInit.MPU_Div = RCC_MPU_DIV2;
256-
// RCC_ClkInitStructure.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
257-
// RCC_ClkInitStructure.AXISSInit.AXI_Div = RCC_AXI_DIV1;
258-
// RCC_ClkInitStructure.MLAHBInit.MLAHB_Clock = RCC_MLAHBSSOURCE_PLL3;
259-
// RCC_ClkInitStructure.MLAHBInit.MLAHB_Div = RCC_MLAHB_DIV1;
260-
// RCC_ClkInitStructure.APB1_Div = RCC_APB1_DIV2;
261-
// RCC_ClkInitStructure.APB2_Div = RCC_APB2_DIV2;
262-
// RCC_ClkInitStructure.APB3_Div = RCC_APB3_DIV2;
263-
// RCC_ClkInitStructure.APB4_Div = RCC_APB4_DIV2;
264-
// RCC_ClkInitStructure.APB5_Div = RCC_APB5_DIV4;
265-
// RCC_ClkInitStructure.APB6_Div = RCC_APB6_DIV2;
266-
267-
// d.on();
268-
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStructure) != HAL_OK) {
269-
// return 0;
270-
// }
271-
// d.off();
272-
273-
// d.on();
274-
// auto sp = HAL_RCC_GetSystemCoreClockFreq();
275-
// d.off();
276-
277-
// return sp;
278139
}
279140
};

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