[nrf fromlist] soc: nordic: Extend address validation for nRF54H20

Upstream PR: zephyrproject-rtos/zephyr#71536

Add `CHECK_DT_REG()` entries for a few additional peripheral types:
BELLBOARD, CCM, GRTC, HSFLL, UICR, and VPR.

For peripheral instances outside of the Global Domain, such as DPPIC020,
use domain-specific defines like NRF_RADIOCORE_DPPIC020 when validating.
These are always defined by the MDK, while NRF_DPPIC020 isn't guaranteed
to exist in those cases. Revise existing macro checks accordingly.

Signed-off-by: Grzegorz Swiderski <[email protected]>
(cherry picked from commit 1750413c7f22a76d504c35a890d31eab469c9850)

Author: 57300

soc/arm/nordic_nrf/validate_base_addresses.c

@@ -36,6 +36,14 @@
 #define NRF_QDEC0 NRF_QDEC
 #endif
 
+#if !defined(NRF_RADIO) && defined(NRF_RADIOCORE_RADIO)
+#define NRF_RADIO NRF_RADIOCORE_RADIO
+#endif
+
+#if !defined(NRF_RTC) && defined(NRF_RADIOCORE_RTC)
+#define NRF_RTC NRF_RADIOCORE_RTC
+#endif
+
 #if !defined(NRF_SWI0) && defined(NRF_SWI_BASE)
 #define NRF_SWI0 ((0 * 0x1000) + NRF_SWI_BASE)
 #endif
@@ -125,8 +133,13 @@
 
 CHECK_DT_REG(acl, NRF_ACL);
 CHECK_DT_REG(adc, NODE_ADDRESS(adc, nordic_nrf_adc, NRF_ADC, NRF_SAADC));
+CHECK_DT_REG(cpusec_bellboard, NRF_SECDOMBELLBOARD);
+CHECK_DT_REG(cpuapp_bellboard, NRF_APPLICATION_BELLBOARD);
+CHECK_DT_REG(cpurad_bellboard, NRF_RADIOCORE_BELLBOARD);
 CHECK_DT_REG(bprot, NRF_BPROT);
 CHECK_DT_REG(ccm, NRF_CCM);
+CHECK_DT_REG(ccm030, NRF_RADIOCORE_CCM030);
+CHECK_DT_REG(ccm031, NRF_RADIOCORE_CCM031);
 CHECK_DT_REG(clock, NRF_CLOCK);
 CHECK_DT_REG(comp, NODE_ADDRESS(comp, nordic_nrf_comp, NRF_COMP, NRF_LPCOMP));
 CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL);
@@ -137,7 +150,7 @@ CHECK_DT_REG(dppic00, NRF_DPPIC00);
 CHECK_DT_REG(dppic10, NRF_DPPIC10);
 CHECK_DT_REG(dppic20, NRF_DPPIC20);
 CHECK_DT_REG(dppic30, NRF_DPPIC30);
-CHECK_DT_REG(dppic020, NRF_DPPIC020);
+CHECK_DT_REG(dppic020, NRF_RADIOCORE_DPPIC020);
 CHECK_DT_REG(dppic120, NRF_DPPIC120);
 CHECK_DT_REG(dppic130, NRF_DPPIC130);
 CHECK_DT_REG(dppic131, NRF_DPPIC131);
@@ -148,7 +161,8 @@ CHECK_DT_REG(dppic135, NRF_DPPIC135);
 CHECK_DT_REG(dppic136, NRF_DPPIC136);
 CHECK_DT_REG(ecb, NRF_ECB);
 CHECK_DT_REG(ecb020, NRF_ECB020);
-CHECK_DT_REG(ecb030, NRF_ECB030);
+CHECK_DT_REG(ecb030, NRF_RADIOCORE_ECB030);
+CHECK_DT_REG(ecb031, NRF_RADIOCORE_ECB031);
 CHECK_DT_REG(egu0, NRF_EGU0);
 CHECK_DT_REG(egu1, NRF_EGU1);
 CHECK_DT_REG(egu2, NRF_EGU2);
@@ -157,7 +171,7 @@ CHECK_DT_REG(egu4, NRF_EGU4);
 CHECK_DT_REG(egu5, NRF_EGU5);
 CHECK_DT_REG(egu10, NRF_EGU10);
 CHECK_DT_REG(egu20, NRF_EGU20);
-CHECK_DT_REG(egu020, NRF_EGU020);
+CHECK_DT_REG(egu020, NRF_RADIOCORE_EGU020);
 CHECK_DT_REG(ficr, NRF_FICR);
 CHECK_DT_REG(flash_controller, NRF_NVMC);
 CHECK_DT_REG(gpio0, NRF_P0);
@@ -173,6 +187,9 @@ CHECK_DT_REG(gpiote20, NRF_GPIOTE20);
 CHECK_DT_REG(gpiote30, NRF_GPIOTE30);
 CHECK_DT_REG(gpiote130, NRF_GPIOTE130);
 CHECK_DT_REG(gpiote131, NRF_GPIOTE131);
+CHECK_DT_REG(grtc, NRF_GRTC);
+CHECK_DT_REG(cpuapp_hsfll, NRF_APPLICATION_HSFLL);
+CHECK_DT_REG(cpurad_hsfll, NRF_RADIOCORE_HSFLL);
 CHECK_I2C_REG(i2c0, 0);
 CHECK_I2C_REG(i2c1, 1);
 CHECK_DT_REG(i2c2, NRF_TWIM2);
@@ -192,8 +209,8 @@ CHECK_DT_REG(i2c137, NRF_TWIM137);
 CHECK_DT_REG(i2s0, NRF_I2S0);
 CHECK_DT_REG(i2s20, NRF_I2S20);
 CHECK_DT_REG(ipc, NRF_IPC);
-CHECK_DT_REG(cpuapp_ipct, NRF_IPCT);
-CHECK_DT_REG(cpurad_ipct, NRF_IPCT);
+CHECK_DT_REG(cpuapp_ipct, NRF_APPLICATION_IPCT);
+CHECK_DT_REG(cpurad_ipct, NRF_RADIOCORE_IPCT);
 CHECK_DT_REG(ipct120, NRF_IPCT120);
 CHECK_DT_REG(ipct130, NRF_IPCT130);
 CHECK_DT_REG(kmu, NRF_KMU);
@@ -274,9 +291,9 @@ CHECK_DT_REG(timer21, NRF_TIMER21);
 CHECK_DT_REG(timer22, NRF_TIMER22);
 CHECK_DT_REG(timer23, NRF_TIMER23);
 CHECK_DT_REG(timer24, NRF_TIMER24);
-CHECK_DT_REG(timer020, NRF_TIMER020);
-CHECK_DT_REG(timer021, NRF_TIMER021);
-CHECK_DT_REG(timer022, NRF_TIMER022);
+CHECK_DT_REG(timer020, NRF_RADIOCORE_TIMER020);
+CHECK_DT_REG(timer021, NRF_RADIOCORE_TIMER021);
+CHECK_DT_REG(timer022, NRF_RADIOCORE_TIMER022);
 CHECK_DT_REG(timer120, NRF_TIMER120);
 CHECK_DT_REG(timer121, NRF_TIMER121);
 CHECK_DT_REG(timer130, NRF_TIMER130);
@@ -306,11 +323,14 @@ CHECK_DT_REG(uart135, NRF_UARTE135);
 CHECK_DT_REG(uart136, NRF_UARTE136);
 CHECK_DT_REG(uart137, NRF_UARTE137);
 CHECK_DT_REG(uicr, NRF_UICR);
+CHECK_DT_REG(cpuapp_uicr, NRF_APPLICATION_UICR);
+CHECK_DT_REG(cpurad_uicr, NRF_RADIOCORE_UICR);
 CHECK_DT_REG(usbd, NRF_USBD);
 CHECK_DT_REG(usbhs, NRF_USBHS);
 CHECK_DT_REG(usbhs_core, NRF_USBHSCORE0);
 CHECK_DT_REG(usbreg, NRF_USBREGULATOR);
 CHECK_DT_REG(vmc, NRF_VMC);
+CHECK_DT_REG(cpuppr_vpr, NRF_VPR130);
 CHECK_DT_REG(wdt, NRF_WDT0);	/* this should be the same node as wdt0 */
 CHECK_DT_REG(wdt0, NRF_WDT0);
 CHECK_DT_REG(wdt1, NRF_WDT1);