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lines changed Original file line number Diff line number Diff line change @@ -1257,6 +1257,8 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
12571257static int bcm2835_clock_determine_rate (struct clk_hw * hw ,
12581258 struct clk_rate_request * req )
12591259{
1260+ struct bcm2835_clock * clock = bcm2835_clock_from_hw (hw );
1261+ struct bcm2835_cprman * cprman = clock -> cprman ;
12601262 struct clk_hw * parent , * best_parent = NULL ;
12611263 bool current_parent_is_pllc ;
12621264 unsigned long rate , best_rate = 0 ;
@@ -1276,13 +1278,17 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
12761278 continue ;
12771279
12781280 /*
1281+ * BCM2835 only.
12791282 * Don't choose a PLLC-derived clock as our parent
12801283 * unless it had been manually set that way. PLLC's
12811284 * frequency gets adjusted by the firmware due to
12821285 * over-temp or under-voltage conditions, without
12831286 * prior notification to our clock consumer.
1287+ * (BCM2711 doesn't do this, therefore it is safe to
1288+ * use PLLC)
12841289 */
1285- if (bcm2835_clk_is_pllc (parent ) && !current_parent_is_pllc )
1290+ if ((cprman -> soc & SOC_BCM2835 ) && bcm2835_clk_is_pllc (parent ) &&
1291+ !current_parent_is_pllc )
12861292 continue ;
12871293
12881294 rate = bcm2835_clock_choose_div_and_prate (hw , i , req -> rate ,
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