@@ -1257,6 +1257,8 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
12571257static int bcm2835_clock_determine_rate (struct clk_hw * hw ,
12581258 struct clk_rate_request * req )
12591259{
1260+ struct bcm2835_clock * clock = bcm2835_clock_from_hw (hw );
1261+ struct bcm2835_cprman * cprman = clock -> cprman ;
12601262 struct clk_hw * parent , * best_parent = NULL ;
12611263 bool current_parent_is_pllc ;
12621264 unsigned long rate , best_rate = 0 ;
@@ -1277,12 +1279,13 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
12771279
12781280 /*
12791281 * Don't choose a PLLC-derived clock as our parent
1280- * unless it had been manually set that way. PLLC's
1281- * frequency gets adjusted by the firmware due to
1282+ * unless it had been manually set that way. On BCM2835,
1283+ * PLLC's frequency gets adjusted by the firmware due to
12821284 * over-temp or under-voltage conditions, without
12831285 * prior notification to our clock consumer.
12841286 */
1285- if (bcm2835_clk_is_pllc (parent ) && !current_parent_is_pllc )
1287+ if ((cprman -> soc & SOC_BCM2835 ) && bcm2835_clk_is_pllc (parent ) &&
1288+ !current_parent_is_pllc )
12861289 continue ;
12871290
12881291 rate = bcm2835_clock_choose_div_and_prate (hw , i , req -> rate ,
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