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lurchlurch
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Latest updates to the autogenerated headers (hathach#1122)
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4 files changed

+71
-66
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4 files changed

+71
-66
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‎src/rp2040/hardware_regs/include/hardware/regs/dma.h‎

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@
8484
// Description : If 1, the channel received a read bus error. Write one to
8585
// clear.
8686
// READ_ADDR shows the approximate address where the bus error was
87-
// encountered (will not to be earlier, or more than 3 transfers
87+
// encountered (will not be earlier, or more than 3 transfers
8888
// later)
8989
#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
9090
#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -96,8 +96,8 @@
9696
// Description : If 1, the channel received a write bus error. Write one to
9797
// clear.
9898
// WRITE_ADDR shows the approximate address where the bus error
99-
// was encountered (will not to be earlier, or more than 5
100-
// transfers later)
99+
// was encountered (will not be earlier, or more than 5 transfers
100+
// later)
101101
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
102102
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
103103
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -472,7 +472,7 @@
472472
// Description : If 1, the channel received a read bus error. Write one to
473473
// clear.
474474
// READ_ADDR shows the approximate address where the bus error was
475-
// encountered (will not to be earlier, or more than 3 transfers
475+
// encountered (will not be earlier, or more than 3 transfers
476476
// later)
477477
#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
478478
#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -484,8 +484,8 @@
484484
// Description : If 1, the channel received a write bus error. Write one to
485485
// clear.
486486
// WRITE_ADDR shows the approximate address where the bus error
487-
// was encountered (will not to be earlier, or more than 5
488-
// transfers later)
487+
// was encountered (will not be earlier, or more than 5 transfers
488+
// later)
489489
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
490490
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
491491
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -860,7 +860,7 @@
860860
// Description : If 1, the channel received a read bus error. Write one to
861861
// clear.
862862
// READ_ADDR shows the approximate address where the bus error was
863-
// encountered (will not to be earlier, or more than 3 transfers
863+
// encountered (will not be earlier, or more than 3 transfers
864864
// later)
865865
#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
866866
#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -872,8 +872,8 @@
872872
// Description : If 1, the channel received a write bus error. Write one to
873873
// clear.
874874
// WRITE_ADDR shows the approximate address where the bus error
875-
// was encountered (will not to be earlier, or more than 5
876-
// transfers later)
875+
// was encountered (will not be earlier, or more than 5 transfers
876+
// later)
877877
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
878878
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
879879
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -1248,7 +1248,7 @@
12481248
// Description : If 1, the channel received a read bus error. Write one to
12491249
// clear.
12501250
// READ_ADDR shows the approximate address where the bus error was
1251-
// encountered (will not to be earlier, or more than 3 transfers
1251+
// encountered (will not be earlier, or more than 3 transfers
12521252
// later)
12531253
#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
12541254
#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -1260,8 +1260,8 @@
12601260
// Description : If 1, the channel received a write bus error. Write one to
12611261
// clear.
12621262
// WRITE_ADDR shows the approximate address where the bus error
1263-
// was encountered (will not to be earlier, or more than 5
1264-
// transfers later)
1263+
// was encountered (will not be earlier, or more than 5 transfers
1264+
// later)
12651265
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
12661266
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
12671267
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -1636,7 +1636,7 @@
16361636
// Description : If 1, the channel received a read bus error. Write one to
16371637
// clear.
16381638
// READ_ADDR shows the approximate address where the bus error was
1639-
// encountered (will not to be earlier, or more than 3 transfers
1639+
// encountered (will not be earlier, or more than 3 transfers
16401640
// later)
16411641
#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
16421642
#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -1648,8 +1648,8 @@
16481648
// Description : If 1, the channel received a write bus error. Write one to
16491649
// clear.
16501650
// WRITE_ADDR shows the approximate address where the bus error
1651-
// was encountered (will not to be earlier, or more than 5
1652-
// transfers later)
1651+
// was encountered (will not be earlier, or more than 5 transfers
1652+
// later)
16531653
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
16541654
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
16551655
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2024,7 +2024,7 @@
20242024
// Description : If 1, the channel received a read bus error. Write one to
20252025
// clear.
20262026
// READ_ADDR shows the approximate address where the bus error was
2027-
// encountered (will not to be earlier, or more than 3 transfers
2027+
// encountered (will not be earlier, or more than 3 transfers
20282028
// later)
20292029
#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
20302030
#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2036,8 +2036,8 @@
20362036
// Description : If 1, the channel received a write bus error. Write one to
20372037
// clear.
20382038
// WRITE_ADDR shows the approximate address where the bus error
2039-
// was encountered (will not to be earlier, or more than 5
2040-
// transfers later)
2039+
// was encountered (will not be earlier, or more than 5 transfers
2040+
// later)
20412041
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
20422042
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
20432043
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2412,7 +2412,7 @@
24122412
// Description : If 1, the channel received a read bus error. Write one to
24132413
// clear.
24142414
// READ_ADDR shows the approximate address where the bus error was
2415-
// encountered (will not to be earlier, or more than 3 transfers
2415+
// encountered (will not be earlier, or more than 3 transfers
24162416
// later)
24172417
#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
24182418
#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2424,8 +2424,8 @@
24242424
// Description : If 1, the channel received a write bus error. Write one to
24252425
// clear.
24262426
// WRITE_ADDR shows the approximate address where the bus error
2427-
// was encountered (will not to be earlier, or more than 5
2428-
// transfers later)
2427+
// was encountered (will not be earlier, or more than 5 transfers
2428+
// later)
24292429
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
24302430
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
24312431
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2800,7 +2800,7 @@
28002800
// Description : If 1, the channel received a read bus error. Write one to
28012801
// clear.
28022802
// READ_ADDR shows the approximate address where the bus error was
2803-
// encountered (will not to be earlier, or more than 3 transfers
2803+
// encountered (will not be earlier, or more than 3 transfers
28042804
// later)
28052805
#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
28062806
#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2812,8 +2812,8 @@
28122812
// Description : If 1, the channel received a write bus error. Write one to
28132813
// clear.
28142814
// WRITE_ADDR shows the approximate address where the bus error
2815-
// was encountered (will not to be earlier, or more than 5
2816-
// transfers later)
2815+
// was encountered (will not be earlier, or more than 5 transfers
2816+
// later)
28172817
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
28182818
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
28192819
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3188,7 +3188,7 @@
31883188
// Description : If 1, the channel received a read bus error. Write one to
31893189
// clear.
31903190
// READ_ADDR shows the approximate address where the bus error was
3191-
// encountered (will not to be earlier, or more than 3 transfers
3191+
// encountered (will not be earlier, or more than 3 transfers
31923192
// later)
31933193
#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
31943194
#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3200,8 +3200,8 @@
32003200
// Description : If 1, the channel received a write bus error. Write one to
32013201
// clear.
32023202
// WRITE_ADDR shows the approximate address where the bus error
3203-
// was encountered (will not to be earlier, or more than 5
3204-
// transfers later)
3203+
// was encountered (will not be earlier, or more than 5 transfers
3204+
// later)
32053205
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
32063206
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
32073207
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3576,7 +3576,7 @@
35763576
// Description : If 1, the channel received a read bus error. Write one to
35773577
// clear.
35783578
// READ_ADDR shows the approximate address where the bus error was
3579-
// encountered (will not to be earlier, or more than 3 transfers
3579+
// encountered (will not be earlier, or more than 3 transfers
35803580
// later)
35813581
#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
35823582
#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3588,8 +3588,8 @@
35883588
// Description : If 1, the channel received a write bus error. Write one to
35893589
// clear.
35903590
// WRITE_ADDR shows the approximate address where the bus error
3591-
// was encountered (will not to be earlier, or more than 5
3592-
// transfers later)
3591+
// was encountered (will not be earlier, or more than 5 transfers
3592+
// later)
35933593
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
35943594
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
35953595
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3964,7 +3964,7 @@
39643964
// Description : If 1, the channel received a read bus error. Write one to
39653965
// clear.
39663966
// READ_ADDR shows the approximate address where the bus error was
3967-
// encountered (will not to be earlier, or more than 3 transfers
3967+
// encountered (will not be earlier, or more than 3 transfers
39683968
// later)
39693969
#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
39703970
#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3976,8 +3976,8 @@
39763976
// Description : If 1, the channel received a write bus error. Write one to
39773977
// clear.
39783978
// WRITE_ADDR shows the approximate address where the bus error
3979-
// was encountered (will not to be earlier, or more than 5
3980-
// transfers later)
3979+
// was encountered (will not be earlier, or more than 5 transfers
3980+
// later)
39813981
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
39823982
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
39833983
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -4352,7 +4352,7 @@
43524352
// Description : If 1, the channel received a read bus error. Write one to
43534353
// clear.
43544354
// READ_ADDR shows the approximate address where the bus error was
4355-
// encountered (will not to be earlier, or more than 3 transfers
4355+
// encountered (will not be earlier, or more than 3 transfers
43564356
// later)
43574357
#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
43584358
#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -4364,8 +4364,8 @@
43644364
// Description : If 1, the channel received a write bus error. Write one to
43654365
// clear.
43664366
// WRITE_ADDR shows the approximate address where the bus error
4367-
// was encountered (will not to be earlier, or more than 5
4368-
// transfers later)
4367+
// was encountered (will not be earlier, or more than 5 transfers
4368+
// later)
43694369
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
43704370
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
43714371
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -4690,7 +4690,7 @@
46904690
#define DMA_INTR_RESET _u(0x00000000)
46914691
#define DMA_INTR_MSB _u(15)
46924692
#define DMA_INTR_LSB _u(0)
4693-
#define DMA_INTR_ACCESS "RO"
4693+
#define DMA_INTR_ACCESS "WC"
46944694
// =============================================================================
46954695
// Register : DMA_INTE0
46964696
// Description : Interrupt Enables for IRQ 0

‎src/rp2040/hardware_regs/include/hardware/regs/pio.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
2+
* Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -52,6 +52,9 @@
5252
// counter; the waiting-on-IRQ state; any stalled instruction
5353
// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
5454
// asserted due to OUT_STICKY.
55+
//
56+
// The program counter, the contents of the output shift register
57+
// and the X/Y scratch registers are not affected.
5558
#define PIO_CTRL_SM_RESTART_RESET _u(0x0)
5659
#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)
5760
#define PIO_CTRL_SM_RESTART_MSB _u(7)

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