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+#### RAID
+
+The full name of RAID is 'redundant array of inexpensive disk'.
+
+#### RAID 1
+The disk are fully duplicated onto its 'mirror'.
+Its effect is to recovery the data which misses in an unexpected way.
+
+#### RAID 3
+We have a new disk called 'parity disk' which is used of recovering the data.
+When the data in the former disk is missing, we can recover the data by add the other data in the disk to calculate the missing data.
+But this method can't recover the data when two disk is failed.
+And it can't read or write two disk in the same time.
+
+#### RAID 4
+Every sector in the disk has a parity which is called 'self parity'.
+It supports small read, but it still only supports large write.
+
+#### RAID 5
+It supports small write by the following method.
+It has interleaved parity which means two parity are in different disks and we modify the parity by $P'=P+D'-D$, so we needn't to read all the disk.
+
+#### A little queuing theory
+$Length_{server} = rate \times Time_{server}$
+
+#### Interconnection
+We define a (n,k) cube is a hybercube with n dimensions and k nodes in every dimension.
+
+The diameter is defined as the maximum of two node's distance(the number of link between them).
+
+It is easy to know that if the same node has the least diameter, then its dimension is the most.
+
+#### multi-stage interconnection network
+![](multistage-interconnection-network-l.jpg)
+
+It solves the problem that the node has too many degree in n cube.
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+- [notes of Bao_chenhao](./W10D1_Bao_chenhao.md) 
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+### Hardware support for exposing more parallelism at compiler-time
+
+We can use predicate version load word(LWC).
+Load occurs unless the third operand is 0.
+
+### Hardware support for memory reference speculation
+
+When we met
+- Store Mx
+- Load My
+  
+We can put load earlier before Store.
+
+But we have one problem, if Mx=My we can just do a check load at the first load space.
+
+### Spinlock 
+A locking mechanism called nonblocking locker.
+It can't sleep while waiting the task.
+
+### Load Link && Store conditional
+
+It can detect that whether `load/store` instruction is **atomic**.
+(transaction memory)
+```
+; swap operation
+; suppose R4 = y, mem[0(R1)] = x
+mov R3, R4		; R3 = y
+ll  R2, 0(R1) ; R2 = x
+sc  R3, 0(R1) ; mem[0(R1)] = y;
+beqz R3, try
+mov R4, R2 		; R4 = x 
+```
+
+```
+ll 	R2, 0(R1)
+addi R2, R2 #1 ; increment
+sc	 R2, 0(R1)
+beqz R2, try
+```
+
+We explain the latter example.
+
+First, if we use the origin load and store, we just increase the value in the memory whose address is R1. But this time if other people modify the value during the load and store, then we will get wrong value.
+
+So we introduce a new register(linker register) to record the address R1, then when we do the store, then we check the register, if the address isn't equal to zero, then we store the value and change the register to zero. Else it fail, we try another time.
+
+We have just one LR register, so we can do ll/sc in ll/sc which called nested ll/sc.
+
+Compare and swap is different from ll/sc because it just compare the value but not pay attention to whether it has been modified.(ABA problem).
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+- [notes of Bao_chenhao](./W13D2_Bao_chenhao.md)  
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