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+## RW : scoreboarding  vs.  Tomasulo
+
+Inventor of scoreboarding : Seymour Cray
+
+renaming : 标注是哪条指令的结果
+
+乱序 ： make FUs busy
+
+Pentinum 处理器 ：放入了所有指令
+
+### 1. Branch (RW : delay slots 填充指令)
+
+Branch Prediction algorithom
+
+思想：
+
+- 历史预测未来
+
+#### 1.1 2-bit Scheme 2位饱和计数器 
+
+思想：迟滞性响应
+
+#### 1.2 corelating Branch Predictors
+
+多个计数器，先通过 hash 确定行
+
+Q：$b_i,b_j$ 对应到同一行？
+
+A：全局计数器，看历史前2条，判断用哪列
+
+#### 1.3 Tournament 锦标赛
+
+基本思想： 多预测器
+
+- global predictor
+- local predictor
+
+
+
+### 2. BHT (data structure to help 1)
+
+branch history table
+
+BTB: branch target buffer
+
+
+
+### 3. special case return addr
+
+例：UALR 实际上难以预测跳到的地址
+
+对 BTB 提出挑战
+
+
+
+### 4. virtual registers
+
+hold both arvhitecturally visible (ASM code visible) + temp. value
+
+e.g. X86 CISC Arch, RISC micro-arch
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+![image-20221227005724987](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227005724987.png)
+
+cache line 要加 tag，一旦被换，直接abort
+
+最好把相关的东西放在一个 cache line
+
+加个tag，别的核修改时，改tag，然后检查tag 就可以判断abort
+
+snoopy协议，检查被abort的line有没有tx标记，有就abort
+
+abort之后跳到abort_handler然后跑，该程序是手动指定的
+
+
+
+![image-20221227205523501](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227205523501.png)
+
+
+
+
+
+addm，xbegin，xend
+
+
+
+细想一下，是不是不用别的核改内存，只要在一个事务里连续访问数组，当访问到一定大小，abort的时候就是cache的大小，虽然这个时候要求别的core不能有干扰（用到时load进cache，之后监测，同样地，如果发生cache冲突，就会产生abort）
+
+
+
+
+
+
+
+
+
+
+
+
+
+![image-20221227011102903](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227011102903.png)
+
+
+
+
+
+1. 如果CPU与L1直接通信，则需要等L1实现核间同步，现在直接放到buffer里，然后CPU继续跑，就不会被卡住
+2. 原因是这个CPU以为已经写入L1实现同步，但实际上可能还没写，别的核用到的可能还是旧值
+3. FIFO可以保证 WAW，非FIFO可能顺序乱掉
+
+
+
+solution：对于自己的buffer和L1 cache，取值要先找自己的buffer
+
+store buffer不对外
+
+![image-20221227012003208](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227012003208.png)
+
+例如起初有x=y=0，
+
+ CPU1 进行 x=1,y=2的操作
+
+CPU2 进行$m = x,n = y$
+
+则符合若内存模型规定的是：
+
+m=0, n=0
+
+m=1,n=0
+
+m=1,n=2
+
+
+
+
+
+
+
+## 冗余存储
+
+![image-20221227133244506](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227133244506.png)
+
+### RAID10
+
+### RAID01
+
+![image-20221227222009791](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227222009791.png)
+
+
+
+实现上的区别
+
+磁盘使用率
+
+容错
+
+![image-20221227133854357](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227133854357.png)
+
+![image-20221227133914064](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227133914064.png)
+
+![image-20221227134432478](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227134432478.png)
+
+初始化raid？处理读指令？
+
+![image-20221227144331553](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227144331553.png)
+
+
+
+### Solution：
+
+所以实际上的意思是我们要用RISCV的指令来实现 disc control 那个CPU的操作。
+然后要做的实际上就是对于一个收到的地址，如果是RAID10，就先用地址取模找到对应磁盘对，
+然后对两路同时load，再进行次按位check？
+
+对于RAID01就对两路都发条load指令？
+但是从哪个盘取到了RAID0这层是不是还得要个CPU来算？
+
+
+
+
+
+## 内存保护键
+
+
+
+## 内存保护键
+
+![image-20221227193236912](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227193236912.png)
+
+标注domine是以页表为单位的，实现对P【100】的越界判定通过把P【100】放在页表最后，保证后项domine不一样
+
+
+
+![image-20221227202804273](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221227202804273.png)
+
+tlb内的地址也会带着 标志domine 的 0010
+
+![image-20221228093502182](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\assets\image-20221228093502182.png)
+
+
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+## Cache
+
+![image-20230113131904863](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\note_doc\assets\image-20230113131904863.png)
+
+
+
+- MR: miss rate
+- MP: miss penalty
+- HT: hit time
+
+
+
+RW: non-blocking Cache ? ( in P83 )
+
+reduce $T_{hit}$: prefetch, outstanding...
+
+需要寄存器：Miss Status Holding Registers
+
+
+
+
+
+##  Virtual Memory
+
+disk 内划分一块作为 mem
+
+### virtual address
+
+![b9809bc2ea3a519a68215e82d562a12](D:\Users\JXGuo\OneDrive\studying_materials\computer_related\computer_arch\note_doc\assets\b9809bc2ea3a519a68215e82d562a12.jpg)
+
+#### Translation
+
+- section
+- segment
+- page
+
+
+
+碎片分类：external fragment, internal fragment
+
+
+
+### Page
+
+- VA : (vp # , offset)
+
+- PA : (physical page # , offset)
+
+- translate : page table in mem
+
+
+
+### 与 Cache 的关系
+
+1. virtual addressing cache ： 歧义 (ambiguity) & 别名 (alias)  
+2. physical addressing cache : 每次访问 Cache 都要翻译，开销大
+
+hint : 当 page 字段够左边，此时不会出问题
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