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Merge tag 'pull-aspeed-20250309' of https://github.com/legoater/qemu into staging
aspeed queue: * Updated Aspeed OpenBMC functional test images * Introduced functional tests for witherspoon and bletchley machines * Added support for Non-maskable Interrupt on AST2700 SoC * Fixed HW strapping on AST2700 SoC * Added AST2700 HACE support * Added AST2700 A1 SoC support * Intoduced new ast2700a1-evb machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmfNnIUACgkQUaNDx8/7 # 7KFMGQ//YHvJV30PkI9CHO6Gbk3CmWftI9Dbjn7goghV/hArVThiq9fve3n2GxYJ # aKrpQZ3BK5SOvcp1zzSc2HrCxmzhy98TZfH2vqwqx3T7uqLDTGgo6xGRYT7+fuVn # SzQaxFJ5hG8LdR4GqDcuUlUVyjVM3ZGR8E/Guj6s6Um1gctZsjy7Z+CdAWDlXFWM # uJoI9EwbhdIWYWF6jJw3myOjMhXHNZs0IobvS7yzZ3DGX0o/P3jRxFYeS6P9lQDl # +TmZ/IRuZDMgA3N+jAyQfMjmlvtA0BygLUbrKTJXb6Bz0BhUjUVahOv6Mnq86yZh # glKCg9LB4BVZneTw5VSd3Tj6Lt/qNhhJjRlV+UYxWzZ0zmFNdkq08RRxKCmMbtYi # t4DsT7xGqfMK9JXEOIWa5REyP4i5llzKe173ml4wSi1Nro9hzZz5cgAKS+7Eabni # nCLhOi26hwkBUCqCKN2eTyRKqOtyftOiKGYog1EV4YtwbnfQS072h0FJz8H6Ibkt # n+twrO8NY31Y0JMzj0GksZ0JSlV/04mtuIpNMSqPizMN/VZPznqwCiaGADtips4f # DoJRtJyDaI/n0IlbtcRpcsrax0uQQEdClvFlcfOkSvkm1aZU2q7wwSKbyOkcnWgd # qnxkUqjHnQTlUSEOqjhtEcw7Bv6J7Mn5IwN0zKROIZp9ia+LZwI= # =O5Kv # -----END PGP SIGNATURE----- # gpg: Signature made Sun 09 Mar 2025 21:49:57 HKT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <[email protected]>" [full] # gpg: aka "Cédric Le Goater <[email protected]>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20250309' of https://github.com/legoater/qemu: (46 commits) docs/specs: Add aspeed-intc tests/functional/aspeed: Add test case for AST2700 A1 tests/functional/aspeed: Update test ASPEED SDK v09.05 tests/functional/aspeed: Update temperature hwmon path tests/functional/aspeed: Introduce start_ast2700_test API hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address hw/arm/aspeed: Add Machine Support for AST2700 A1 hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1 hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions hw/intc/aspeed: Add Support for AST2700 INTCIO Controller hw/intc/aspeed: Add Support for Multi-Output IRQ Handling hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address hw/intc/aspeed: Refactor INTC to support separate input and output pin indices hw/intc/aspeed: Add support for multiple output pins in INTC hw/intc/aspeed: Rename num_ints to num_inpins for clarity hw/intc/aspeed: Support different memory region ops ... Signed-off-by: Stefan Hajnoczi <[email protected]>
2 parents 1843a0c + 5ab179d commit 2e14ac3

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‎docs/specs/aspeed-intc.rst

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@@ -0,0 +1,136 @@
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===========================
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ASPEED Interrupt Controller
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===========================
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AST2700
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-------
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There are a total of 480 interrupt sources in AST2700. Due to the limitation of
8+
interrupt numbers of processors, the interrupts are merged every 32 sources for
9+
interrupt numbers greater than 127.
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There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO
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(I/O Die).
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Interrupt Mapping
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-----------------
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- INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO.
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- INTCIO: Handles interrupt sources 128 - 319 independently.
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QEMU Support
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------------
21+
Currently, only GIC 192 to 201 are supported, and their source interrupts are
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from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
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GIC 192-201.
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Design for GICINT 196
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---------------------
27+
The orgate has interrupt sources ranging from 0 to 31, with its output pin
28+
connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC
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"GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196.
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INTC GIC_192_201 Output Pin Mapping
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-----------------------------------
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The design of INTC GIC_192_201 have 10 output pins, mapped as following:
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==== ====
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Bit GIC
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==== ====
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0 192
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1 193
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2 194
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3 195
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4 196
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5 197
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6 198
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7 199
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8 200
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9 201
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==== ====
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AST2700 A0
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----------
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It has only one INTC controller, and currently, only GIC 128-136 is supported.
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To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the INTC,
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with gates 1 to 9 supporting GIC 128-136.
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Design for GICINT 132
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---------------------
58+
The orgate has interrupt sources ranging from 0 to 31, with its output pin
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connected to INTC. The output pin is then connected to GIC 132.
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Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0
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------------------------------------------------------------------------
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.. code-block::
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|-------------------------------------------------------------------------------------------------------|
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| AST2700 A1 Design |
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| To GICINT196 |
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| |
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| ETH1 |-----------| |--------------------------| |--------------| |
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| -------->|0 | | INTCIO | | orgates[0] | |
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| ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
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| -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
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| ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
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| -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
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| UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
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| -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
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| UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
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| -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
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| UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
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| -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
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| UART3 | 26| |--------------------------| |--------------| | |
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| ---------|10 27| | |
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| UART5 | 28| | |
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| -------->|11 29| | |
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| UART6 | | | |
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| -------->|12 30| |-----------------------------------------------------------------------| |
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| UART7 | 31| | |
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| -------->|13 | | |
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| UART8 | OR[0:31] | | |------------------------------| |----------| |
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| -------->|14 | | | INTC | | GIC | |
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| UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
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| -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
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| UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
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| -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
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| UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
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| -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
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| UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
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| -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
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| |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
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| |inpin[0:9]--------->outpin[9] |---------->|201 | |
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|-------------------------------------------------------------------------------------------------------|
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|-------------------------------------------------------------------------------------------------------|
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| ETH1 |-----------| orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | |
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| -------->|0 | orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | |
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| ETH2 | 4| orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | |
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| -------->|1 5| orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | |
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| ETH3 | 6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132 | |
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| -------->|2 19| orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | |
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| UART0 | 20| orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | |
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| -------->|7 21| orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | |
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| UART1 | 22| orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | |
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| -------->|8 23| |------------------------------| |----------| |
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| UART2 | 24| |
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| -------->|9 25| AST2700 A0 Design |
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| UART3 | 26| |
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| -------->|10 27| |
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| UART5 | 28| |
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| -------->|11 29| GICINT132 |
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| UART6 | | |
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| -------->|12 30| |
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| UART7 | 31| |
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| -------->|13 | |
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| UART8 | OR[0:31] | |
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| -------->|14 | |
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| UART9 | | |
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| -------->|15 | |
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| UART10 | | |
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| -------->|16 | |
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| UART11 | | |
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| -------->|17 | |
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| UART12 | | |
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| -------->|18 | |
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| |-----------| |
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| |
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|-------------------------------------------------------------------------------------------------------|

‎docs/specs/index.rst

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@@ -38,3 +38,4 @@ guest hardware that is specific to QEMU.
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rocker
3939
riscv-iommu
4040
riscv-aia
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aspeed-intc

‎hw/arm/aspeed.c

Lines changed: 33 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -181,8 +181,10 @@ struct AspeedMachineState {
181181

182182
#ifdef TARGET_AARCH64
183183
/* AST2700 evb hardware value */
184-
#define AST2700_EVB_HW_STRAP1 0x000000C0
185-
#define AST2700_EVB_HW_STRAP2 0x00000003
184+
/* SCU HW Strap1 */
185+
#define AST2700_EVB_HW_STRAP1 0x00000800
186+
/* SCUIO HW Strap1 */
187+
#define AST2700_EVB_HW_STRAP2 0x00000700
186188
#endif
187189

188190
/* Rainier hardware value: (QEMU prototype) */
@@ -1671,12 +1673,13 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
16711673
TYPE_TMP105, 0x4d);
16721674
}
16731675

1674-
static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
1676+
static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
16751677
{
16761678
MachineClass *mc = MACHINE_CLASS(oc);
16771679
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
16781680

1679-
mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
1681+
mc->alias = "ast2700-evb";
1682+
mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
16801683
amc->soc_name = "ast2700-a0";
16811684
amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
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amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
@@ -1690,6 +1693,26 @@ static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
16901693
mc->default_ram_size = 1 * GiB;
16911694
aspeed_machine_class_init_cpus_defaults(mc);
16921695
}
1696+
1697+
static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data)
1698+
{
1699+
MachineClass *mc = MACHINE_CLASS(oc);
1700+
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1701+
1702+
mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
1703+
amc->soc_name = "ast2700-a1";
1704+
amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1705+
amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1706+
amc->fmc_model = "w25q01jvq";
1707+
amc->spi_model = "w25q512jv";
1708+
amc->num_cs = 2;
1709+
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1710+
amc->uart_default = ASPEED_DEV_UART12;
1711+
amc->i2c_init = ast2700_evb_i2c_init;
1712+
mc->auto_create_sdcard = true;
1713+
mc->default_ram_size = 1 * GiB;
1714+
aspeed_machine_class_init_cpus_defaults(mc);
1715+
}
16931716
#endif
16941717

16951718
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
@@ -1815,9 +1838,13 @@ static const TypeInfo aspeed_machine_types[] = {
18151838
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
18161839
#ifdef TARGET_AARCH64
18171840
}, {
1818-
.name = MACHINE_TYPE_NAME("ast2700-evb"),
1841+
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
1842+
.parent = TYPE_ASPEED_MACHINE,
1843+
.class_init = aspeed_machine_ast2700a0_evb_class_init,
1844+
}, {
1845+
.name = MACHINE_TYPE_NAME("ast2700a1-evb"),
18191846
.parent = TYPE_ASPEED_MACHINE,
1820-
.class_init = aspeed_machine_ast2700_evb_class_init,
1847+
.class_init = aspeed_machine_ast2700a1_evb_class_init,
18211848
#endif
18221849
}, {
18231850
.name = TYPE_ASPEED_MACHINE,

‎hw/arm/aspeed_ast10x0.c

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Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
116116
char typename[64];
117117
int i;
118118

119-
if (sscanf(sc->name, "%7s", socname) != 1) {
119+
if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
120120
g_assert_not_reached();
121121
}
122122

@@ -428,7 +428,6 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
428428
dc->user_creatable = false;
429429
dc->realize = aspeed_soc_ast1030_realize;
430430

431-
sc->name = "ast1030-a1";
432431
sc->valid_cpu_types = valid_cpu_types;
433432
sc->silicon_rev = AST1030_A1_SILICON_REV;
434433
sc->sram_size = 0xc0000;

‎hw/arm/aspeed_ast2400.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
151151
char socname[8];
152152
char typename[64];
153153

154-
if (sscanf(sc->name, "%7s", socname) != 1) {
154+
if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
155155
g_assert_not_reached();
156156
}
157157

@@ -515,7 +515,6 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
515515
/* Reason: Uses serial_hds and nd_table in realize() directly */
516516
dc->user_creatable = false;
517517

518-
sc->name = "ast2400-a1";
519518
sc->valid_cpu_types = valid_cpu_types;
520519
sc->silicon_rev = AST2400_A1_SILICON_REV;
521520
sc->sram_size = 0x8000;
@@ -544,7 +543,6 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
544543
/* Reason: Uses serial_hds and nd_table in realize() directly */
545544
dc->user_creatable = false;
546545

547-
sc->name = "ast2500-a1";
548546
sc->valid_cpu_types = valid_cpu_types;
549547
sc->silicon_rev = AST2500_A1_SILICON_REV;
550548
sc->sram_size = 0x9000;

‎hw/arm/aspeed_ast2600.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
157157
char socname[8];
158158
char typename[64];
159159

160-
if (sscanf(sc->name, "%7s", socname) != 1) {
160+
if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
161161
g_assert_not_reached();
162162
}
163163

@@ -666,7 +666,6 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
666666
/* Reason: The Aspeed SoC can only be instantiated from a board */
667667
dc->user_creatable = false;
668668

669-
sc->name = "ast2600-a3";
670669
sc->valid_cpu_types = valid_cpu_types;
671670
sc->silicon_rev = AST2600_A3_SILICON_REV;
672671
sc->sram_size = 0x16400;

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