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Andrey ShumilinMichael Tokarev
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hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>
In gic_cpu_read() and gic_cpu_write(), we delegate the handling of reading and writing the Non-Secure view of the GICC_APR<n> registers to functions gic_apr_ns_view() and gic_apr_write_ns_view(). Unfortunately we got the order of the arguments wrong, swapping the CPU number and the register number (which the compiler doesn't catch because they're both integers). Most guests probably didn't notice this bug because directly accessing the APR registers is typically something only done by firmware when it is doing state save for going into a sleep mode. Correct the mismatched call arguments. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: [email protected] Fixes: 51fd06e ("hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers") Signed-off-by: Andrey Shumilin <[email protected]> [PMM: Rewrote commit message] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Alex Bennée<[email protected]> (cherry picked from commit daafa78) Signed-off-by: Michael Tokarev <[email protected]>
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hw/intc/arm_gic.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1658,7 +1658,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
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*data = s->h_apr[gic_get_vcpu_real_id(cpu)];
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} else if (gic_cpu_ns_access(s, cpu, attrs)) {
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/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1661-
*data = gic_apr_ns_view(s, regno, cpu);
1661+
*data = gic_apr_ns_view(s, cpu, regno);
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} else {
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*data = s->apr[regno][cpu];
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}
@@ -1746,7 +1746,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
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s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
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} else if (gic_cpu_ns_access(s, cpu, attrs)) {
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/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1749-
gic_apr_write_ns_view(s, regno, cpu, value);
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gic_apr_write_ns_view(s, cpu, regno, value);
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} else {
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s->apr[regno][cpu] = value;
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}

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