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hw/rtc: Add Ricoh RS5C372 RTC emulation
The implementation just allows Linux to determine date and time. Signed-off-by: Bernhard Beschow <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Acked-by: Fabiano Rosas <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
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‎MAINTAINERS

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@@ -827,10 +827,12 @@ F: hw/arm/imx8mp-evk.c
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F: hw/arm/fsl-imx8mp.c
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F: hw/misc/imx8mp_*.c
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F: hw/pci-host/fsl_imx8m_phy.c
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F: hw/rtc/rs5c372.c
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F: include/hw/arm/fsl-imx8mp.h
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F: include/hw/misc/imx8mp_*.h
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F: include/hw/pci-host/fsl_imx8m_phy.h
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F: docs/system/arm/imx8mp-evk.rst
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F: tests/qtest/rs5c372-test.c
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MPS2 / MPS3
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M: Peter Maydell <[email protected]>

‎hw/rtc/Kconfig

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@@ -26,3 +26,8 @@ config GOLDFISH_RTC
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config LS7A_RTC
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bool
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config RS5C372_RTC
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bool
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depends on I2C
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default y if I2C_DEVICES

‎hw/rtc/meson.build

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@@ -13,3 +13,4 @@ system_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true: files('goldfish_rtc.c'))
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system_ss.add(when: 'CONFIG_LS7A_RTC', if_true: files('ls7a_rtc.c'))
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system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c'))
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system_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c'))
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system_ss.add(when: 'CONFIG_RS5C372_RTC', if_true: files('rs5c372.c'))

‎hw/rtc/rs5c372.c

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/*
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* Ricoh RS5C372, R222x I2C RTC
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*
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* Copyright (c) 2025 Bernhard Beschow <[email protected]>
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*
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* Based on hw/rtc/ds1338.c
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/i2c/i2c.h"
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#include "hw/qdev-properties.h"
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#include "hw/resettable.h"
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#include "migration/vmstate.h"
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#include "qemu/bcd.h"
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#include "qom/object.h"
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#include "system/rtc.h"
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#include "trace.h"
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#define NVRAM_SIZE 0x10
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/* Flags definitions */
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#define SECONDS_CH 0x80
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#define HOURS_PM 0x20
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#define CTRL2_24 0x20
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#define TYPE_RS5C372 "rs5c372"
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OBJECT_DECLARE_SIMPLE_TYPE(RS5C372State, RS5C372)
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struct RS5C372State {
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I2CSlave parent_obj;
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int64_t offset;
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uint8_t wday_offset;
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uint8_t nvram[NVRAM_SIZE];
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uint8_t ptr;
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uint8_t tx_format;
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bool addr_byte;
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};
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static void capture_current_time(RS5C372State *s)
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{
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/*
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* Capture the current time into the secondary registers which will be
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* actually read by the data transfer operation.
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*/
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struct tm now;
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qemu_get_timedate(&now, s->offset);
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s->nvram[0] = to_bcd(now.tm_sec);
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s->nvram[1] = to_bcd(now.tm_min);
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if (s->nvram[0xf] & CTRL2_24) {
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s->nvram[2] = to_bcd(now.tm_hour);
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} else {
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int tmp = now.tm_hour;
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if (tmp % 12 == 0) {
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tmp += 12;
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}
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if (tmp <= 12) {
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s->nvram[2] = to_bcd(tmp);
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} else {
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s->nvram[2] = HOURS_PM | to_bcd(tmp - 12);
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}
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}
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s->nvram[3] = (now.tm_wday + s->wday_offset) % 7 + 1;
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s->nvram[4] = to_bcd(now.tm_mday);
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s->nvram[5] = to_bcd(now.tm_mon + 1);
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s->nvram[6] = to_bcd(now.tm_year - 100);
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}
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static void inc_regptr(RS5C372State *s)
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{
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s->ptr = (s->ptr + 1) & (NVRAM_SIZE - 1);
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}
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static int rs5c372_event(I2CSlave *i2c, enum i2c_event event)
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{
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RS5C372State *s = RS5C372(i2c);
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switch (event) {
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case I2C_START_RECV:
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/*
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* In h/w, capture happens on any START condition, not just a
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* START_RECV, but there is no need to actually capture on
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* START_SEND, because the guest can't get at that data
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* without going through a START_RECV which would overwrite it.
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*/
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capture_current_time(s);
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s->ptr = 0xf;
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break;
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case I2C_START_SEND:
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s->addr_byte = true;
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break;
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default:
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break;
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}
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return 0;
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}
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static uint8_t rs5c372_recv(I2CSlave *i2c)
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{
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RS5C372State *s = RS5C372(i2c);
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uint8_t res;
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res = s->nvram[s->ptr];
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trace_rs5c372_recv(s->ptr, res);
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inc_regptr(s);
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return res;
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}
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static int rs5c372_send(I2CSlave *i2c, uint8_t data)
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{
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RS5C372State *s = RS5C372(i2c);
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if (s->addr_byte) {
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s->ptr = data >> 4;
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s->tx_format = data & 0xf;
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s->addr_byte = false;
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return 0;
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}
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trace_rs5c372_send(s->ptr, data);
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if (s->ptr < 7) {
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/* Time register. */
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struct tm now;
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qemu_get_timedate(&now, s->offset);
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switch (s->ptr) {
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case 0:
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now.tm_sec = from_bcd(data & 0x7f);
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break;
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case 1:
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now.tm_min = from_bcd(data & 0x7f);
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break;
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case 2:
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if (s->nvram[0xf] & CTRL2_24) {
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now.tm_hour = from_bcd(data & 0x3f);
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} else {
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int tmp = from_bcd(data & (HOURS_PM - 1));
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if (data & HOURS_PM) {
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tmp += 12;
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}
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if (tmp % 12 == 0) {
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tmp -= 12;
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}
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now.tm_hour = tmp;
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}
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break;
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case 3:
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{
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/*
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* The day field is supposed to contain a value in the range
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* 1-7. Otherwise behavior is undefined.
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*/
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int user_wday = (data & 7) - 1;
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s->wday_offset = (user_wday - now.tm_wday + 7) % 7;
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}
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break;
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case 4:
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now.tm_mday = from_bcd(data & 0x3f);
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break;
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case 5:
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now.tm_mon = from_bcd(data & 0x1f) - 1;
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break;
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case 6:
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now.tm_year = from_bcd(data) + 100;
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break;
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}
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s->offset = qemu_timedate_diff(&now);
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} else {
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s->nvram[s->ptr] = data;
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}
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inc_regptr(s);
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return 0;
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}
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static void rs5c372_reset_hold(Object *obj, ResetType type)
181+
{
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RS5C372State *s = RS5C372(obj);
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/* The clock is running and synchronized with the host */
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s->offset = 0;
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s->wday_offset = 0;
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memset(s->nvram, 0, NVRAM_SIZE);
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s->ptr = 0;
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s->addr_byte = false;
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}
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static const VMStateDescription rs5c372_vmstate = {
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.name = "rs5c372",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_I2C_SLAVE(parent_obj, RS5C372State),
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VMSTATE_INT64(offset, RS5C372State),
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VMSTATE_UINT8_V(wday_offset, RS5C372State, 2),
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VMSTATE_UINT8_ARRAY(nvram, RS5C372State, NVRAM_SIZE),
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VMSTATE_UINT8(ptr, RS5C372State),
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VMSTATE_UINT8(tx_format, RS5C372State),
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VMSTATE_BOOL(addr_byte, RS5C372State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void rs5c372_init(Object *obj)
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{
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qdev_prop_set_uint8(DEVICE(obj), "address", 0x32);
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}
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static void rs5c372_class_init(ObjectClass *klass, void *data)
214+
{
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DeviceClass *dc = DEVICE_CLASS(klass);
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I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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k->event = rs5c372_event;
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k->recv = rs5c372_recv;
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k->send = rs5c372_send;
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dc->vmsd = &rs5c372_vmstate;
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rc->phases.hold = rs5c372_reset_hold;
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}
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static const TypeInfo rs5c372_types[] = {
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{
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.name = TYPE_RS5C372,
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.parent = TYPE_I2C_SLAVE,
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.instance_size = sizeof(RS5C372State),
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.instance_init = rs5c372_init,
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.class_init = rs5c372_class_init,
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},
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};
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DEFINE_TYPES(rs5c372_types)

‎hw/rtc/trace-events

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@@ -35,3 +35,7 @@ m48txx_nvram_mem_write(uint32_t addr, uint32_t value) "mem write addr:0x%04x val
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# goldfish_rtc.c
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goldfish_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
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goldfish_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
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# rs5c372.c
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rs5c372_recv(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] -> 0x%02" PRIx8
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rs5c372_send(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] <- 0x%02" PRIx8

‎tests/qtest/meson.build

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@@ -298,6 +298,7 @@ qos_test_ss.add(
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'pca9552-test.c',
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'pci-test.c',
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'pcnet-test.c',
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'rs5c372-test.c',
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'sdhci-test.c',
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'spapr-phb-test.c',
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'tmp105-test.c',

‎tests/qtest/rs5c372-test.c

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/*
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* QTest testcase for the RS5C372 RTC
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*
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* Copyright (c) 2025 Bernhard Beschow <[email protected]>
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*
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* Based on ds1338-test.c
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/bcd.h"
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#include "libqos/i2c.h"
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#define RS5C372_ADDR 0x32
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static void rs5c372_read_date(void *obj, void *data, QGuestAllocator *alloc)
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{
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QI2CDevice *i2cdev = obj;
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uint8_t resp[0x10];
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time_t now = time(NULL);
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struct tm *utc = gmtime(&now);
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i2c_read_block(i2cdev, 0, resp, sizeof(resp));
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/* check retrieved time against local time */
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g_assert_cmpuint(from_bcd(resp[5]), == , utc->tm_mday);
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g_assert_cmpuint(from_bcd(resp[6]), == , 1 + utc->tm_mon);
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g_assert_cmpuint(2000 + from_bcd(resp[7]), == , 1900 + utc->tm_year);
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}
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static void rs5c372_register_nodes(void)
34+
{
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QOSGraphEdgeOptions opts = { };
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add_qi2c_address(&opts, &(QI2CAddress) { RS5C372_ADDR });
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qos_node_create_driver("rs5c372", i2c_device_create);
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qos_node_consumes("rs5c372", "i2c-bus", &opts);
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qos_add_test("read_date", "rs5c372", rs5c372_read_date, NULL);
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}
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libqos_init(rs5c372_register_nodes);

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