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Alexei FilippovMichael Tokarev
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target/riscv: do not set mtval2 for non guest-page faults
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage translation part, mtval2 will be set in case of successes 2 stage translation but failed pmp check. In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest page-fault is taken into M-mode, mtval2 is written with either zero or guest physical address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* Signed-off-by: Alexei Filippov <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Cc: qemu-stable <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit 6c9a344) Signed-off-by: Michael Tokarev <[email protected]>
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target/riscv/cpu_helper.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1375,17 +1375,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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__func__, pa, ret, prot_pmp, tlb_size);
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prot &= prot_pmp;
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}
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if (ret != TRANSLATE_SUCCESS) {
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} else {
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/*
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* Guest physical address translation failed, this is a HS
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* level exception
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*/
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first_stage_error = false;
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env->guest_phys_fault_addr = (im_address |
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(address &
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(TARGET_PAGE_SIZE - 1))) >> 2;
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if (ret != TRANSLATE_PMP_FAIL) {
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env->guest_phys_fault_addr = (im_address |
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(address &
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(TARGET_PAGE_SIZE - 1))) >> 2;
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}
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}
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}
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} else {

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