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author
Dil4rd
committed
mips64 support
1 parent b91d3e2 commit 5fee52e

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4 files changed

+74
-30
lines changed

4 files changed

+74
-30
lines changed

‎qemuafl/api.h

Lines changed: 61 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,26 @@
33

44
#include <stdint.h>
55

6+
#if defined(TARGET_MIPS64) || defined(TARGET_AARCH64) || defined(TARGET_X86_64)
7+
# define TARGET_LONG_BITS 64
8+
#else
9+
# define TARGET_LONG_BITS 32
10+
#endif
11+
12+
/* see include/exec/cpu-defs.h */
13+
#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
14+
15+
#if TARGET_LONG_SIZE == 4
16+
typedef int32_t target_long;
17+
typedef uint32_t target_ulong;
18+
#elif TARGET_LONG_SIZE == 8
19+
typedef int64_t target_long;
20+
typedef uint64_t target_ulong;
21+
#else
22+
#error TARGET_LONG_SIZE undefined
23+
#endif
24+
25+
626
struct x86_regs {
727

828
uint32_t eax, ebx, ecx, edx, edi, esi, ebp;
@@ -138,13 +158,49 @@ struct arm64_regs {
138158
};
139159

140160
/* MIPS_PATCH */
141-
#if defined(TARGET_MIPS)
161+
#if defined(TARGET_MIPS) || defined(TARGET_MIPS64)
162+
163+
// check standalone usage
164+
// if smth in pers hook goes wrong, check constants below with target/mips/cpu.h
165+
#ifndef MIPS_CPU_H
166+
#include <stdbool.h>
167+
#include "../include/fpu/softfloat-types.h"
168+
169+
/* MSA Context */
170+
#define MSA_WRLEN (128)
171+
typedef union wr_t wr_t;
172+
union wr_t {
173+
int8_t b[MSA_WRLEN / 8];
174+
int16_t h[MSA_WRLEN / 16];
175+
int32_t w[MSA_WRLEN / 32];
176+
int64_t d[MSA_WRLEN / 64];
177+
};
178+
typedef union fpr_t fpr_t;
179+
union fpr_t {
180+
float64 fd; /* ieee double precision */
181+
float32 fs[2];/* ieee single precision */
182+
uint64_t d; /* binary double fixed-point */
183+
uint32_t w[2]; /* binary single fixed-point */
184+
/* FPU/MSA register mapping is not tested on big-endian hosts. */
185+
wr_t wr; /* vector data */
186+
};
187+
#define MIPS_DSP_ACC 4
188+
#endif
189+
142190
struct mips_regs {
143-
uint32_t r0, at, v0, v1, a0, a1, a2, a3, t0, t1, t2, t3, t4, t5, t6, t7, s0,
191+
target_ulong r0, at, v0, v1, a0, a1, a2, a3, t0, t1, t2, t3, t4, t5, t6, t7, s0,
144192
s1, s2, s3, s4, s5, s6, s7, t8, t9, k0, k1, gp, sp, fp, ra;
145-
uint32_t HI[4];
146-
uint32_t LO[4];
147-
uint32_t PC;
193+
#if defined(TARGET_MIPS64)
194+
/*
195+
* For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
196+
* and the upper halves in gpr_hi[].
197+
*/
198+
uint64_t gpr_hi[32];
199+
#endif /* TARGET_MIPS64 */
200+
target_ulong HI[MIPS_DSP_ACC];
201+
target_ulong LO[MIPS_DSP_ACC];
202+
target_ulong ACX[MIPS_DSP_ACC];
203+
target_ulong PC;
148204
fpr_t fpr[32];
149205
};
150206
#endif

‎qemuafl/common.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
#elif defined(TARGET_ARM)
5252
#define api_regs arm_regs
5353
/* MIPS_PATCH */
54-
#elif defined(TARGET_MIPS)
54+
#elif defined(TARGET_MIPS) || defined(TARGET_MIPS64)
5555
#define api_regs mips_regs
5656
#else
5757
struct generic_api_regs { int v; };
@@ -137,7 +137,7 @@ void afl_float_compcov_log_80(target_ulong cur_loc, floatx80 arg1,
137137
abi_ulong afl_get_brk(void);
138138
abi_ulong afl_set_brk(abi_ulong new_brk);
139139

140-
#if defined(TARGET_X86_64) || defined(TARGET_I386) || defined(TARGET_AARCH64) || defined(TARGET_ARM) || defined(TARGET_MIPS)
140+
#if defined(TARGET_X86_64) || defined(TARGET_I386) || defined(TARGET_AARCH64) || defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_MIPS64)
141141
void afl_save_regs(struct api_regs* regs, CPUArchState* env);
142142
void afl_restore_regs(struct api_regs* regs, CPUArchState* env);
143143
#else

‎qemuafl/qasan-qemu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ extern __thread struct shadow_stack qasan_shadow_stack;
8484
#define SP_GET(env) ((env)->aarch64 ? (env)->xregs[31] : (env)->regs[13])
8585

8686
/* MIPS_PATCH */
87-
#elif defined(TARGET_MIPS)
87+
#elif defined(TARGET_MIPS) || defined(TARGET_MIPS64)
8888

8989
#define PC_GET(env) ((env)->active_tc.PC)
9090
#define BP_GET(env) ((env)->active_tc.gpr[29])

‎target/mips/translate.c

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -2296,7 +2296,7 @@ static const char * const mxuregnames[] = {
22962296
#endif
22972297

22982298
/* MIPS_PATCH */
2299-
void afl_save_regs(struct api_regs *r, CPUArchState *env) {
2299+
void afl_save_regs(struct api_regs* r, CPUArchState *env) {
23002300
int i = 0;
23012301
int j = 0;
23022302
/* GP registers saving */
@@ -2333,7 +2333,10 @@ void afl_save_regs(struct api_regs *r, CPUArchState *env) {
23332333
r->fp = env->active_tc.gpr[30];
23342334
r->ra = env->active_tc.gpr[31];
23352335
r->PC = env->active_tc.PC;
2336-
for (i = 0; i < 4; i++) {
2336+
#if defined(TARGET_MIPS64)
2337+
memcpy(r->gpr_hi, env->active_tc.gpr_hi, sizeof(r->gpr_hi));
2338+
#endif
2339+
for (i = 0; i < MIPS_DSP_ACC; i++) {
23372340
r->HI[i] = env->active_tc.HI[i];
23382341
r->LO[i] = env->active_tc.LO[i];
23392342
}
@@ -2350,20 +2353,11 @@ void afl_save_regs(struct api_regs *r, CPUArchState *env) {
23502353
for (j = 0; j < MSA_WRLEN / 8; j++) {
23512354
r->fpr[i].wr.b[j] = env->active_fpu.fpr[i].wr.b[j];
23522355
}
2353-
for (j = 0; j < MSA_WRLEN / 16; j++) {
2354-
r->fpr[i].wr.h[j] = env->active_fpu.fpr[i].wr.h[j];
2355-
}
2356-
for (j = 0; j < MSA_WRLEN / 32; j++) {
2357-
r->fpr[i].wr.w[j] = env->active_fpu.fpr[i].wr.w[j];
2358-
}
2359-
for (j = 0; j < MSA_WRLEN / 64; j++) {
2360-
r->fpr[i].wr.d[j] = env->active_fpu.fpr[i].wr.d[j];
2361-
}
23622356
}
23632357
}
23642358

23652359
/* MIPS_PATCH */
2366-
void afl_restore_regs(struct api_regs *r, CPUArchState *env) {
2360+
void afl_restore_regs(struct api_regs* r, CPUArchState *env) {
23672361
int i = 0;
23682362
int j = 0;
23692363
/* GP registers restoring */
@@ -2400,7 +2394,10 @@ void afl_restore_regs(struct api_regs *r, CPUArchState *env) {
24002394
env->active_tc.gpr[30] = r->fp;
24012395
env->active_tc.gpr[31] = r->ra;
24022396
env->active_tc.PC = r->PC;
2403-
for (i = 0; i < 4; i++) {
2397+
#if defined(TARGET_MIPS64)
2398+
memcpy(env->active_tc.gpr_hi, r->gpr_hi, sizeof(r->gpr_hi));
2399+
#endif
2400+
for (i = 0; i < MIPS_DSP_ACC; i++) {
24042401
env->active_tc.HI[i] = r->HI[i];
24052402
env->active_tc.LO[i] = r->LO[i];
24062403
}
@@ -2417,15 +2414,6 @@ void afl_restore_regs(struct api_regs *r, CPUArchState *env) {
24172414
for (j = 0; j < MSA_WRLEN / 8; j++) {
24182415
env->active_fpu.fpr[i].wr.b[j] = r->fpr[i].wr.b[j];
24192416
}
2420-
for (j = 0; j < MSA_WRLEN / 16; j++) {
2421-
env->active_fpu.fpr[i].wr.h[j] = r->fpr[i].wr.h[j];
2422-
}
2423-
for (j = 0; j < MSA_WRLEN / 32; j++) {
2424-
env->active_fpu.fpr[i].wr.w[j] = r->fpr[i].wr.w[j];
2425-
}
2426-
for (j = 0; j < MSA_WRLEN / 64; j++) {
2427-
env->active_fpu.fpr[i].wr.d[j] = r->fpr[i].wr.d[j];
2428-
}
24292417
}
24302418
}
24312419

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