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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' into staging
Initial commit for the Qualcomm Hexagon processor. # gpg: Signature made Thu 18 Feb 2021 16:26:52 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "[email protected]" # gpg: Good signature from "Richard Henderson <[email protected]>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-hex-20210218: (35 commits) Hexagon build infrastructure Hexagon (tests/tcg/hexagon) TCG tests - floating point Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Hexagon (tests/tcg/hexagon) TCG tests - multiarch Hexagon (linux-user/hexagon) Linux user emulation Hexagon (target/hexagon) translation Hexagon (target/hexagon) TCG for floating point instructions Hexagon (target/hexagon) TCG for instructions with multiple definitions Hexagon (target/hexagon) TCG generation Hexagon (target/hexagon) instruction classes Hexagon (target/hexagon) macros Hexagon (target/hexagon) opcode data structures Hexagon (target/hexagon) generater phase 4 - decode tree Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Hexagon (target/hexagon) generator phase 2 - generate header files Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Hexagon (target/hexagon/imported) arch import Hexagon (target/hexagon/fma_emu.[ch]) utility functions Hexagon (target/hexagon/conv_emu.[ch]) utility functions Hexagon (target/hexagon/arch.[ch]) utility functions ... Signed-off-by: Peter Maydell <[email protected]>
2 parents b826fb8 + 3e7a84e commit c79f01c

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lines changed

‎MAINTAINERS

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@@ -188,6 +188,15 @@ F: include/hw/cris/
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F: tests/tcg/cris/
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F: disas/cris.c
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Hexagon TCG CPUs
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M: Taylor Simpson <[email protected]>
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S: Supported
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F: target/hexagon/
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F: linux-user/hexagon/
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F: tests/tcg/hexagon/
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F: disas/hexagon.c
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F: default-configs/targets/hexagon-linux-user.mak
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HPPA (PA-RISC) TCG CPUs
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M: Richard Henderson <[email protected]>
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S: Maintained

‎default-configs/targets/hexagon-linux-user.mak

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TARGET_ARCH=hexagon

‎disas/hexagon.c

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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* QEMU Hexagon Disassembler
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*/
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#include "qemu/osdep.h"
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#include "disas/dis-asm.h"
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#include "target/hexagon/cpu_bits.h"
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/*
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* We will disassemble a packet with up to 4 instructions, so we need
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* a hefty size buffer.
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*/
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#define PACKET_BUFFER_LEN 1028
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int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
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{
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uint32_t words[PACKET_WORDS_MAX];
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bool found_end = false;
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GString *buf = g_string_sized_new(PACKET_BUFFER_LEN);
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int i, len;
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for (i = 0; i < PACKET_WORDS_MAX && !found_end; i++) {
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int status = (*info->read_memory_func)(memaddr + i * sizeof(uint32_t),
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(bfd_byte *)&words[i],
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sizeof(uint32_t), info);
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if (status) {
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if (i > 0) {
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break;
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}
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(*info->memory_error_func)(status, memaddr, info);
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return status;
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}
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if (is_packet_end(words[i])) {
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found_end = true;
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}
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}
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if (!found_end) {
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(*info->fprintf_func)(info->stream, "<invalid>");
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return PACKET_WORDS_MAX * sizeof(uint32_t);
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}
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len = disassemble_hexagon(words, i, memaddr, buf);
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(*info->fprintf_func)(info->stream, "%s", buf->str);
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g_string_free(buf, true);
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return len;
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}

‎disas/meson.build

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@@ -6,6 +6,7 @@ common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc'))
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common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss)
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common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c'))
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common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
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common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
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common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
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common_ss.add(when: 'CONFIG_I386_DIS', if_true: files('i386.c'))
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common_ss.add(when: 'CONFIG_LM32_DIS', if_true: files('lm32.c'))

‎include/disas/dis-asm.h

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@@ -459,6 +459,7 @@ int print_insn_xtensa (bfd_vma, disassemble_info*);
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int print_insn_riscv32 (bfd_vma, disassemble_info*);
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int print_insn_riscv64 (bfd_vma, disassemble_info*);
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int print_insn_rx(bfd_vma, disassemble_info *);
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int print_insn_hexagon(bfd_vma, disassemble_info *);
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#ifdef CONFIG_CAPSTONE
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bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size);

‎include/elf.h

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@@ -176,6 +176,7 @@ typedef struct mips_elf_abiflags_v0 {
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#define EM_UNICORE32 110 /* UniCore32 */
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#define EM_HEXAGON 164 /* Qualcomm Hexagon */
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#define EM_RX 173 /* Renesas RX family */
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#define EM_RISCV 243 /* RISC-V */

‎include/qemu/int128.h

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@@ -58,6 +58,11 @@ static inline Int128 int128_and(Int128 a, Int128 b)
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return a & b;
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}
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static inline Int128 int128_or(Int128 a, Int128 b)
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{
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return a | b;
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}
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static inline Int128 int128_rshift(Int128 a, int n)
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{
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return a >> n;
@@ -208,6 +213,11 @@ static inline Int128 int128_and(Int128 a, Int128 b)
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return (Int128) { a.lo & b.lo, a.hi & b.hi };
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}
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static inline Int128 int128_or(Int128 a, Int128 b)
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{
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return (Int128) { a.lo | b.lo, a.hi | b.hi };
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}
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static inline Int128 int128_rshift(Int128 a, int n)
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{
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int64_t h;

‎linux-user/elfload.c

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@@ -1514,6 +1514,22 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
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#endif /* TARGET_XTENSA */
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#ifdef TARGET_HEXAGON
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#define ELF_START_MMAP 0x20000000
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#define ELF_CLASS ELFCLASS32
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#define ELF_ARCH EM_HEXAGON
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1524+
static inline void init_thread(struct target_pt_regs *regs,
1525+
struct image_info *infop)
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{
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regs->sepc = infop->entry;
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regs->sp = infop->start_stack;
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}
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1531+
#endif /* TARGET_HEXAGON */
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#ifndef ELF_PLATFORM
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#define ELF_PLATFORM (NULL)
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#endif

‎linux-user/hexagon/cpu_loop.c

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/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
10+
* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
13+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15+
* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
19+
*/
20+
21+
#include "qemu/osdep.h"
22+
#include "qemu.h"
23+
#include "cpu_loop-common.h"
24+
#include "internal.h"
25+
26+
void cpu_loop(CPUHexagonState *env)
27+
{
28+
CPUState *cs = CPU(hexagon_env_get_cpu(env));
29+
int trapnr, signum, sigcode;
30+
target_ulong sigaddr;
31+
target_ulong syscallnum;
32+
target_ulong ret;
33+
34+
for (;;) {
35+
cpu_exec_start(cs);
36+
trapnr = cpu_exec(cs);
37+
cpu_exec_end(cs);
38+
process_queued_cpu_work(cs);
39+
40+
signum = 0;
41+
sigcode = 0;
42+
sigaddr = 0;
43+
44+
switch (trapnr) {
45+
case EXCP_INTERRUPT:
46+
/* just indicate that signals should be handled asap */
47+
break;
48+
case HEX_EXCP_TRAP0:
49+
syscallnum = env->gpr[6];
50+
env->gpr[HEX_REG_PC] += 4;
51+
ret = do_syscall(env,
52+
syscallnum,
53+
env->gpr[0],
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env->gpr[1],
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env->gpr[2],
56+
env->gpr[3],
57+
env->gpr[4],
58+
env->gpr[5],
59+
0, 0);
60+
if (ret == -TARGET_ERESTARTSYS) {
61+
env->gpr[HEX_REG_PC] -= 4;
62+
} else if (ret != -TARGET_QEMU_ESIGRETURN) {
63+
env->gpr[0] = ret;
64+
}
65+
break;
66+
case HEX_EXCP_FETCH_NO_UPAGE:
67+
case HEX_EXCP_PRIV_NO_UREAD:
68+
case HEX_EXCP_PRIV_NO_UWRITE:
69+
signum = TARGET_SIGSEGV;
70+
sigcode = TARGET_SEGV_MAPERR;
71+
break;
72+
case EXCP_ATOMIC:
73+
cpu_exec_step_atomic(cs);
74+
break;
75+
default:
76+
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
77+
trapnr);
78+
exit(EXIT_FAILURE);
79+
}
80+
81+
if (signum) {
82+
target_siginfo_t info = {
83+
.si_signo = signum,
84+
.si_errno = 0,
85+
.si_code = sigcode,
86+
._sifields._sigfault._addr = sigaddr
87+
};
88+
queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
89+
}
90+
91+
process_pending_signals(env);
92+
}
93+
}
94+
95+
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
96+
{
97+
env->gpr[HEX_REG_PC] = regs->sepc;
98+
env->gpr[HEX_REG_SP] = regs->sp;
99+
env->gpr[HEX_REG_USR] = 0x56000;
100+
}

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