+M. Morris Mano, Digital Logic & Computer . & Computer.Design, 4/e, Pearson Education, 2013 . Digital Electronics: Digital Electronics. The output of a combinational circuit depends on its present. only the present. Only the past inputs of a Sequential circuit . Digital circuits (Digital Circuits) are of two types. Combinational Circuits. Sequential Circuits (Digital . Electronics) Digital Electronics is of two type. Digital Electronics (19-204-0302) The procedure involves the following steps: The problem is stated. The number of available input variables and required output variables is determined. The input and output variables are assigned lettersymbols. The truth table that defines the required relationship between inputs and outputs is defined. The simplified Boolean function for each output is obtained. The logic diagram is drawn. The most basic arithmetic operation is the addition of two binary digits . The logic gates accept signals from the inputs and generate signals to the outputs. They are called Adder Circuits . Adder Circuits are of two types: half-adder and full-adder . The truth table and block diagram of a halfadder is shown below . Realization using AOI logic is possible using one X-OR gate and one AND gate as shown in Figure 7.3a. The full Adder circuit can be realized by using one gate and the other using a single AND gate . The full-adder circuit is a combinational circuit that performs the addition of three bits (two significant bits) The Full-Adder is a combinational circuit that adds two bits and a carry and outputs a sum bit and a carrying bit . The full-adder adds the bits A and B and the carry-in C in and outputs the sum bit S . The Half-adder is a half-adder using only 2-input NOR gates . The Full Adder adds the bit A and A and C in the previous column called the carry in C in, the carry out the other bit called the carrying-in-Cin . AOBOCin.Cout= BCin + A Cin + ABin + ABCin = AB + (AOB) Cout= (AB) + AB = C₁ (A @ B) - CinS = AO BỌCin = (A) (AB), (A@B) (A/B) Cin = A + AOB) = A. (A), (C) (C), (B) + (C/A) C/AOB = (AB/A/C/B/C) and (AO/AOO/C: AOB/Cin/C; (A: A/A: C) C: (C: C: A: A./A; A: C; C: C./C. A half-subtractor is a combinational circuit that subtracts one bit from the other and produces the difference . It also has an output to specify if a 1 has been borrowed . It is used to subtract LSB of the subtrahend from LSB when one binary number is subtracted from the minuend . The circuit is also used to add LSB to the LSB and LSB of a given binary number when one bit is subtracted from one to one and produces a difference . The Full-Subtractor subtracts one bit (B) from another bit (A), when already there is a borrow b, from this column for the subtraction in the preceding column, and outputs the difference bit (d) and the borrow bit (b) required from the next column . A full-subtractor is a combinational circuit with three-inputs (A, B, b.) and two outputs d and b. It can, therefore, be realized using X-OR gates and AOI gates . An n-bit parallel adder is a digital circuit that adds two binary numbers in parallel form . It consists of full adders connected in a chain, with the output carry of each full-adder connected to the input carry of the next fulladder in the chain . The output carry is the output of a full subtractor using only 2-input NAND gates. ure 7.17. bi**d=A0B0b.0b;. - - B- referred to a full-subtractor using only two-input NOR gates. The carry-out of each full-adder is the carry-in to the next most significant stage of a ripple carry adder . The carry out of each stage is connected to the carry in of the next stage . This is due to the propagation delays in the logic-circuitry, which lead to a time delay in the addition process . er requires n-full adders. er needs n-adders. The carry propagation delay is the time between the application and the occurrence of the carry out . The subtraction A - B can be done by taking the 2's complement of B and adding it to A . The subtracted bit is not valid until after the cumulative propagation of two full adders (FA, and FA), and so on . The total sum (the parallel output) of a 4-bit binary adder-subtractor is not . The 1's complement can be implemented with inverters, such as Cout 4, Cout 3, Cin 4 and Cin 2 Cout . When M = 0, the circuit is an adder, and when M = 1, it becomes a subtractor . The speed with which an addition can be performed is governed by the time it takes for the carries to propagate or ripple through the stages of the adder . The full-adder receives the value of a fulladder, the value is O and the circuit performs A + B + B. The circuit performs the operation A plus the 2's complement of B. It performs the addition and subtraction operations of the fulladder . The look-ahead-carry adder speeds up the process by eliminating this ripple carry delay . It examines all the input bits simultaneously and also generates the carry-in bits for all the stages simultaneously . The method of speeding up the addition process is based on the two additional functions of the full-adder, called the carry generate and carry-propagate functions . The full adder is made of two half-adders and the half-adder contains an X-OR gate to produce the sum and an AND gate . The input carry Cn has to be propagated to the output only if Pn is 1 or both Gn and Pn are equal to 1 . The carry-in to each stage is the carry-out of the previous stage . For the final sum and carry outputs of the nth stage, we get the following Boolean expressions: Pn, Cn, P_, Pn-Cn-Sn, P-Sn and C-Sn . The X-OR gate in the second half-adder will inhibit Cn and P-C . The general expression for n stages designated as 0 through (n-1) would be: "Cn Gn-1 + Pn" The expressions for the carry-outs of various full-fledgedadders are: "Go + P1. P1," "C₁," "P1. Go + P2," "Po. Co," "Co," "Gn-2" and "Co-1" are examples of the BCD Adder circuit . The circuit must be able to do the following: Add the 4-bit BCD code groups for each decimal digit position using ordinary binary addition . The circuitry for a BCD adder must include the logic needed to detect whenever the sum is greater than 01001 (decimal 9) so that the correction can be added in . The first requirement is easily met by using a 4-bit binary-centric parallel adder . The sum output can range anywhere from 00000 to 10010 (when both the BCD code groups are 1001 = 9) The circuitry must include logic needed for the logic . The circuitry can be expressed as X = S4 + S3( S2 + S1) or S1 (sums 10 to 15) A code converter is a logic circuit whose inputs are bit-patterns representing numbers (or characters) in one code and whose outputs are the corresponding representations in a different code . The input to the 4-bit binary-to-Gray-code conversion circuit is a 4-Bit binary and the output is a Gray-type code . A code conversion table is a conversion table with the input and output of a 4 bit binary to Gray-style code converter . The output of the converted code table is B4-bit G4 G3 G₂ . The input to a 4-bit-Gray-to-Binary code converter is a 4 bit Gray code . The output is a four-bit Gray code and the input to the code is a 2-bit Gcode . The input is a Gray code with the output a 4bit binary code . A 4 bit Gcode converter would be called a "4-bit" Gcode Converter. The input and output are 4-bits Gcode. The output of a GCode Converter is 4 bits GCode. The code is 4bits GCode . A decoder is a logic circuit that converts an N-bit-binary input code into M output lines . Only one output line is activated for each one of the possible combinations of inputs . Decoder does this because only one input line is high for each of the N inputs can be a 0 or a 1, there are two possible input combinations o. Decoder is called a "decoder" where only one output is activated per line of the code is activated . Figure 7.68 is a block diagram of a decoder . A 3-line to 8-line decoder has three input lines and eight output lines . It is also called a binary-to-octal decoder because it takes a 3-bit binary input code and activates one of the eight (octal) outputs corresponding to that code . Some decoders have one or more ENABLE inputs that are used to control the operation of the decoder . The ABC-Dg decoder takes a three-line input line and eight input lines . In the 3-line to 8-line decoder, a particular output as determined by the A, B, C input of each gate will go HIGH only when the ENABLE line is held high . When a common line is connected to a gate, all the outputs will be forced to the LOW state regardless of the levels at the gate . An example, in Figure 7.70, a common.ENABLE line will be connected to the fourth input of the gate, and the output of that line will go High . The most significant input bit A3 is connected through an inverter to on the upper decoder (for DO through D7) and directly to E on the lower decoder . The bottom decoder outputs generate minterms 1000-to-1111 while the top decoder is all Os . The opposite of the decoding process is called encoding . An encoder is a device whose inputs are decimal digits and/oralphabetic characters and whose outputs are the coded representations of those inputs . The top 8 decoder outputs all Os, and top 8 outputs create minterms . An octal-to-binary encoder accepts 8 input lines, only one of which is activated at a given time, and produces an N-bit output code depending on which input is activated . A2 is a 1 if any of the digits D4 or D5 or D6 or D7 is a '1' and A1 = D2 + D3 + D6 + D7 and D i is 'don't care' because D i isn't present in any expressions . Decimal-to-BCD encoder has 10 inputs- one for each digit, and 4 outputs corresponding to the BCD code . Figure 7.63 is a basic 10-line to 4-line encoder . Multiplexer or data selector is a logic circuit that accepts several data inputs and allows only one of them to get through to the output . AO = D1 + D3 + D4 + D5 + D6 + D7; D7 = D8 + D9; D9 + D8 = D9 . A demultiplexer is a digital circuit that takes a single input and distributes it over several outputs . Magnitude Comparator is a logic circuit that compares two quantities and gives an output signal indicating whether the two input quantities are equal or not . The comparator A is greater than B (8> 4) and if not, which of them is greater . The binary representations of the binary representations are shown in the figure . The figure is based on the 1-to-N device. It is called DeMultiplexer (DeMux) The figure illustrates comparison of 8 and 4, and the result is HIGH (8 > 4) The result is the result of the comparison of A and B, A = B or A > B, depending on the magnitude of the input quantities . The figure is based on the fact that A is A. and B is A, A is B, B is B . The result of comparison of the two quantities is A + B is a result of A being A or B, or A = A, or B + A is an output .
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