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31 | 31 |
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32 | 32 | #define NPS_MODE_MASK 0x000000FFL
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33 | 33 |
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34 |
| -/* Core 0 Port 0 counter */ |
35 |
| -#define smnPCIEP_NAK_COUNTER 0x1A340218 |
36 |
| - |
37 | 34 | static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
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38 | 35 | {
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39 | 36 | WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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@@ -467,22 +464,6 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
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467 | 464 | }
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468 | 465 | }
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469 | 466 |
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470 |
| -static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev) |
471 |
| -{ |
472 |
| - u32 val, nak_r, nak_g; |
473 |
| - |
474 |
| - if (adev->flags & AMD_IS_APU) |
475 |
| - return 0; |
476 |
| - |
477 |
| - /* Get the number of NAKs received and generated */ |
478 |
| - val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); |
479 |
| - nak_r = val & 0xFFFF; |
480 |
| - nak_g = val >> 16; |
481 |
| - |
482 |
| - /* Add the total number of NAKs, i.e the number of replays */ |
483 |
| - return (nak_r + nak_g); |
484 |
| -} |
485 |
| - |
486 | 467 | #define MMIO_REG_HOLE_OFFSET 0x1A000
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487 | 468 |
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488 | 469 | static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
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@@ -524,7 +505,6 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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524 | 505 | .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
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525 | 506 | .is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested,
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526 | 507 | .init_registers = nbio_v7_9_init_registers,
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527 |
| - .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count, |
528 | 508 | .set_reg_remap = nbio_v7_9_set_reg_remap,
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529 | 509 | };
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530 | 510 |
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