UPSTREAM: riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree

The sg2042 SoCs support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1]
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2]

Signed-off-by: Han Gao <[email protected]>
Reviewed-by: Inochi Amaoto <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
(cherry picked from commit a5fb905)
Signed-off-by: Han Gao <[email protected]>

Author: RevySR