FROMLIST: usb: phy: tegra: Add 38.4MHz clock table entry

The Tegra210 uses a 38.4MHz OSC. This clock table entry is required to
use the ehci phy on the Jetson TX1.

The xtal_freq_count is actually a 12 bit value, so it should be a u16
instead of u8.

Signed-off-by: Hunter Laux <[email protected]>

Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Kexy Biscuit <[email protected]>

Author: Hunter Laux

drivers/usb/phy/phy-tegra-usb.c

@@ -174,7 +174,7 @@ struct tegra_xtal_freq {
 	u8 enable_delay;
 	u8 stable_count;
 	u8 active_delay;
-	u8 xtal_freq_count;
+	u16 xtal_freq_count;
 	u16 debounce;
 };
 
@@ -211,6 +211,14 @@ static const struct tegra_xtal_freq tegra_freq_table[] = {
 		.xtal_freq_count = 0xFE,
 		.debounce = 0xFDE8,
 	},
+	{
+		.freq = 38400000,
+		.enable_delay = 0x00,
+		.stable_count = 0x00,
+		.active_delay = 0x18,
+		.xtal_freq_count = 0x177,
+		.debounce = 0xBB80,
+	},
 };
 
 static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)