AOSCOS: Optimize clear_page

Signed-off-by: chenj <[email protected]>
Signed-off-by: Kexy Biscuit <[email protected]>

Author: chenj

arch/mips/include/asm/uasm.h

@@ -42,6 +42,10 @@ void uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 #define Ip_s3s1s2(op)							\
 void uasm_i##op(u32 **buf, int a, int b, int c)
 
+#define Ip_u4u2u1s3(op)						\
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c, \
+	   unsigned int d)
+
 #define Ip_u2u1s3(op)							\
 void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
@@ -159,6 +163,7 @@ Ip_u2s3u1(_sd);
 Ip_u3u1u2(_seleqz);
 Ip_u3u1u2(_selnez);
 Ip_u2s3u1(_sh);
+Ip_u4u2u1s3(_gssq);
 Ip_u2u1u3(_sll);
 Ip_u3u2u1(_sllv);
 Ip_s3s1s2(_slt);

arch/mips/include/uapi/asm/inst.h

@@ -137,6 +137,13 @@ enum ddivu_op {
 	ddivu_dmodu_op = 0x3,
 };
 
+/*
+ * func field of spec opcode.
+ */
+enum swc2_op {
+	gssq_op = 0x20,
+};
+
 /*
  * rt field of bcond opcodes.
  */

arch/mips/mm/page.c

@@ -206,6 +206,11 @@ static void set_prefetch_parameters(void)
 		else if (cpu_has_cache_cdex_p)
 			cache_line_size = cpu_dcache_line_size();
 	}
+
+#ifdef CONFIG_CPU_LOONGSON3
+	clear_word_size = 16;
+#endif
+
 	/*
 	 * Too much unrolling will overflow the available space in
 	 * clear_space_array / copy_page_array.
@@ -220,11 +225,15 @@ static void set_prefetch_parameters(void)
 
 static void build_clear_store(u32 **buf, int off)
 {
+#ifdef CONFIG_CPU_LOONGSON3
+	uasm_i_gssq(buf, ZERO, ZERO, off, A0);
+#else
 	if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
 		uasm_i_sd(buf, GPR_ZERO, off, GPR_A0);
 	} else {
 		uasm_i_sw(buf, GPR_ZERO, off, GPR_A0);
 	}
+#endif
 }
 
 static inline void build_clear_pref(u32 **buf, int off)

arch/mips/mm/uasm-mips.c

@@ -27,6 +27,10 @@
 #define RT_SH		16
 #define SCIMM_MASK	0xfffff
 #define SCIMM_SH	6
+#define RZ_MASK		0x1f
+#define RZ_SH		0
+#define RC_MASK		0x1ff
+#define RC_SH		6
 
 /* This macro sets the non-variable bits of an instruction. */
 #define M(a, b, c, d, e, f)					\
@@ -203,6 +207,7 @@ static const struct insn insn_table[insn_invalid] = {
 	[insn_xor]	= {M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD},
 	[insn_xori]	= {M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM},
 	[insn_yield]	= {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
+	[insn_gssq]	= {M(swc2_op, 0, 0, 0, 0, gssq_op), RT | RS | RZ | RC},
 };
 
 #undef M
@@ -225,6 +230,21 @@ static inline u32 build_jimm(u32 arg)
 	return (arg >> 2) & JIMM_MASK;
 }
 
+static inline u32 build_rz(u32 arg)
+{
+	WARN(arg & ~RZ_MASK, KERN_WARNING "Micro-assembler field overflow\n");
+
+	return (arg & RZ_MASK) << RZ_SH;
+}
+
+static inline u32 build_rc(s32 arg)
+{
+	WARN((arg >> 4) > 0xff ||
+	     (arg >> 4) < -0x100, KERN_WARNING "Micro-assembler field overflow\n");
+
+	return ((arg >> 4) & RC_MASK) << RC_SH;
+}
+
 /*
  * The order of opcode arguments is implicitly left to right,
  * starting with RS and ending with FUNC or IMM.
@@ -252,6 +272,10 @@ static void build_insn(u32 **buf, enum opcode opc, ...)
 		op |= build_rd(va_arg(ap, u32));
 	if (ip->fields & RE)
 		op |= build_re(va_arg(ap, u32));
+	if (ip->fields & RZ)
+		op |= build_rz(va_arg(ap, u32));
+	if (ip->fields & RC)
+		op |= build_rc(va_arg(ap, s32));
 	if (ip->fields & SIMM)
 		op |= build_simm(va_arg(ap, s32));
 	if (ip->fields & UIMM)

arch/mips/mm/uasm.c

@@ -26,6 +26,8 @@ enum fields {
 	SET = 0x200,
 	SCIMM = 0x400,
 	SIMM9 = 0x800,
+	RZ = 0x1000,
+	RC = 0x2000
 };
 
 #define OP_MASK		0x3f
@@ -65,7 +67,7 @@ enum opcode {
 	insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
 	insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
 	insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
-	insn_wsbh, insn_xor, insn_xori, insn_yield,
+	insn_wsbh, insn_xor, insn_xori, insn_yield, insn_gssq,
 	insn_invalid /* insn_invalid must be last */
 };
 
@@ -198,6 +200,13 @@ Ip_u2s3u1(op)						\
 }							\
 UASM_EXPORT_SYMBOL(uasm_i##op);
 
+#define I_u4u2u1s3(op)					\
+Ip_u4u2u1s3(op)						\
+{							\
+	build_insn(buf, insn##op, d, b, a, c);		\
+}							\
+UASM_EXPORT_SYMBOL(uasm_i##op);
+
 #define I_u2u1s3(op)					\
 Ip_u2u1s3(op)						\
 {							\
@@ -356,6 +365,7 @@ I_u2s3u1(_sd)
 I_u3u1u2(_seleqz)
 I_u3u1u2(_selnez)
 I_u2s3u1(_sh)
+I_u4u2u1s3(_gssq)
 I_u2u1u3(_sll)
 I_u3u2u1(_sllv)
 I_s3s1s2(_slt)