From 146ed8924597737309faa026fc5d7adb4f2672bf Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:50:51 +0800 Subject: [PATCH 01/30] Revert "FROMLIST: PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent()" This reverts commit 07b64e9d29cc0d27c70a0d7f8366d95401b19db1. --- drivers/pci/msi/irqdomain.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index b11b7f63f0d6fc..e0a800f918e812 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -154,8 +154,6 @@ static void cond_shutdown_parent(struct irq_data *data) if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) irq_chip_shutdown_parent(data); - else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT)) - irq_chip_mask_parent(data); } static unsigned int cond_startup_parent(struct irq_data *data) @@ -164,9 +162,6 @@ static unsigned int cond_startup_parent(struct irq_data *data) if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) return irq_chip_startup_parent(data); - else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT)) - irq_chip_unmask_parent(data); - return 0; } From a6c368719ba89b870db9ae945e40df2a963a8ccb Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:50:54 +0800 Subject: [PATCH 02/30] Revert "FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup" This reverts commit 14b3fb2642ea9b6323f9297ce4bb024539baefbf. --- arch/riscv/Kconfig.errata | 17 ---------- arch/riscv/errata/thead/errata.c | 20 ------------ arch/riscv/include/asm/errata_list_vendors.h | 3 +- arch/riscv/include/asm/rwonce.h | 34 -------------------- include/asm-generic/rwonce.h | 2 -- 5 files changed, 1 insertion(+), 75 deletions(-) delete mode 100644 arch/riscv/include/asm/rwonce.h diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index d2c982ba537304..e318119d570de0 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -130,21 +130,4 @@ config ERRATA_THEAD_GHOSTWRITE If you don't know what to do here, say "Y". -config ERRATA_THEAD_WRITE_ONCE - bool "Apply T-Head WRITE_ONCE errata" - depends on ERRATA_THEAD - default y - help - The early version of T-Head C9xx cores of sg2042 & th1520 have a store - merge buffer delay problem. The store merge buffer could improve the - store queue performance by merging multi-store requests, but when there - are no continued store requests, the prior single store request would be - waiting in the store queue for a long time. That would cause signifi- - cant problems for communication between multi-cores. Appending a - fence w.o could immediately flush the store merge buffer and let other - cores see the write result. - - This will apply the WRITE_ONCE errata to handle the non-standard beh- - avior via appending a fence w.o instruction for WRITE_ONCE(). - endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index fbe46f2fa8fbbd..0b942183f708fe 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -168,23 +168,6 @@ static bool errata_probe_ghostwrite(unsigned int stage, return true; } -static bool errata_probe_write_once(unsigned int stage, - unsigned long arch_id, unsigned long impid) -{ - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) - return false; - - /* target-c9xx cores report arch_id and impid as 0 */ - if (arch_id != 0 || impid != 0) - return false; - - if (stage == RISCV_ALTERNATIVES_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; - - return false; -} - static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -200,9 +183,6 @@ static u32 thead_errata_probe(unsigned int stage, errata_probe_ghostwrite(stage, archid, impid); - if (errata_probe_write_once(stage, archid, impid)) - cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); - return cpu_req_errata; } diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h index a7473cb8874d62..a37d1558f39fad 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -18,8 +18,7 @@ #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_WRITE_ONCE 3 -#define ERRATA_THEAD_NUMBER 4 +#define ERRATA_THEAD_NUMBER 3 #endif #endif diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h deleted file mode 100644 index 081793d4d772da..00000000000000 --- a/arch/riscv/include/asm/rwonce.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __ASM_RWONCE_H -#define __ASM_RWONCE_H - -#include -#include -#include -#include - -#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) - -#define write_once_fence() \ -do { \ - asm volatile(ALTERNATIVE( \ - "nop", \ - "fence w, o", \ - THEAD_VENDOR_ID, \ - ERRATA_THEAD_WRITE_ONCE, \ - CONFIG_ERRATA_THEAD_WRITE_ONCE) \ - : : : "memory"); \ -} while (0) - -#define __WRITE_ONCE(x, val) \ -do { \ - *(volatile typeof(x) *)&(x) = (val); \ - write_once_fence(); \ -} while (0) - -#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ - -#include - -#endif /* __ASM_RWONCE_H */ diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 4e2d941f15a11b..52b969c7cef935 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -50,12 +50,10 @@ __READ_ONCE(x); \ }) -#ifndef __WRITE_ONCE #define __WRITE_ONCE(x, val) \ do { \ *(volatile typeof(x) *)&(x) = (val); \ } while (0) -#endif #define WRITE_ONCE(x, val) \ do { \ From aa3cc336688d8950e2a8929031d7404d963c8bff Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:50:56 +0800 Subject: [PATCH 03/30] Revert "FROMLIST: riscv: Move vendor errata definitions to new header" This reverts commit 761e9c68298b74677f605860d445d9452be1eec8. --- arch/riscv/include/asm/errata_list.h | 19 +++++++++++++++- arch/riscv/include/asm/errata_list_vendors.h | 24 -------------------- 2 files changed, 18 insertions(+), 25 deletions(-) delete mode 100644 arch/riscv/include/asm/errata_list_vendors.h diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 18c9f7ee9b7c45..6e426ed7919a4a 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -10,7 +10,24 @@ #include #include #include -#include + +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 +#endif + +#ifdef CONFIG_ERRATA_SIFIVE +#define ERRATA_SIFIVE_CIP_453 0 +#define ERRATA_SIFIVE_CIP_1200 1 +#define ERRATA_SIFIVE_NUMBER 2 +#endif + +#ifdef CONFIG_ERRATA_THEAD +#define ERRATA_THEAD_MAE 0 +#define ERRATA_THEAD_PMU 1 +#define ERRATA_THEAD_GHOSTWRITE 2 +#define ERRATA_THEAD_NUMBER 3 +#endif #ifdef __ASSEMBLY__ diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h deleted file mode 100644 index a37d1558f39fad..00000000000000 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef ASM_ERRATA_LIST_VENDORS_H -#define ASM_ERRATA_LIST_VENDORS_H - -#ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDES_NO_IOCP 0 -#define ERRATA_ANDES_NUMBER 1 -#endif - -#ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 -#endif - -#ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_MAE 0 -#define ERRATA_THEAD_PMU 1 -#define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 -#endif - -#endif From 315b0165dc82d43c01b5a38a306d1194b88ea461 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:50:58 +0800 Subject: [PATCH 04/30] Revert "FROMLIST: irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flags for SG2044" This reverts commit 7fd853918530af4c60547490b595d63cbf67d30d. --- drivers/irqchip/irq-sg2042-msi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-msi.c index 3b13dbbfdb51c0..2fd4d94f9bd76d 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -212,7 +212,6 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = { MSI_FLAG_PCI_MSI_STARTUP_PARENT) #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ - MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX) static const struct msi_parent_ops sg2044_msi_parent_ops = { From 0e936ba03610eb7a0f5eb60c66b549b8bc0ac98d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:00 +0800 Subject: [PATCH 05/30] Revert "FROMLIST: irqchip/sg2042-msi: Fix broken affinity setting" This reverts commit 1361f635b24a52abbc69181dccb17ac061b39794. --- drivers/irqchip/irq-sg2042-msi.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-msi.c index 2fd4d94f9bd76d..bcfddc51bc6a18 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -85,8 +85,6 @@ static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *m static const struct irq_chip sg2042_msi_middle_irq_chip = { .name = "SG2042 MSI", - .irq_startup = irq_chip_startup_parent, - .irq_shutdown = irq_chip_shutdown_parent, .irq_ack = sg2042_msi_irq_ack, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, @@ -116,8 +114,6 @@ static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *m static struct irq_chip sg2044_msi_middle_irq_chip = { .name = "SG2044 MSI", - .irq_startup = irq_chip_startup_parent, - .irq_shutdown = irq_chip_shutdown_parent, .irq_ack = sg2044_msi_irq_ack, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, @@ -189,10 +185,8 @@ static const struct irq_domain_ops sg204x_msi_middle_domain_ops = { .select = msi_lib_irq_domain_select, }; -#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS | \ - MSI_FLAG_PCI_MSI_MASK_PARENT | \ - MSI_FLAG_PCI_MSI_STARTUP_PARENT) +#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK @@ -206,12 +200,10 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = { .init_dev_msi_info = msi_lib_init_dev_msi_info, }; -#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS | \ - MSI_FLAG_PCI_MSI_MASK_PARENT | \ - MSI_FLAG_PCI_MSI_STARTUP_PARENT) +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) -#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ MSI_FLAG_PCI_MSIX) static const struct msi_parent_ops sg2044_msi_parent_ops = { From 6f10a570d6095e8a929abd84ba2fe3e77449961a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:02 +0800 Subject: [PATCH 06/30] Revert "FROMLIST: PCI/MSI: Add startup/shutdown for per device domains" This reverts commit 666e16e385f64ae814baeca4f6cb5052688cfd47. --- drivers/pci/msi/irqdomain.c | 52 ------------------------------------- include/linux/msi.h | 2 -- 2 files changed, 54 deletions(-) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index e0a800f918e812..0938ef7ebabf2d 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -148,23 +148,6 @@ static void pci_device_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *d arg->hwirq = desc->msi_index; } -static void cond_shutdown_parent(struct irq_data *data) -{ - struct msi_domain_info *info = data->domain->host_data; - - if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) - irq_chip_shutdown_parent(data); -} - -static unsigned int cond_startup_parent(struct irq_data *data) -{ - struct msi_domain_info *info = data->domain->host_data; - - if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) - return irq_chip_startup_parent(data); - return 0; -} - static __always_inline void cond_mask_parent(struct irq_data *data) { struct msi_domain_info *info = data->domain->host_data; @@ -181,23 +164,6 @@ static __always_inline void cond_unmask_parent(struct irq_data *data) irq_chip_unmask_parent(data); } -static void pci_irq_shutdown_msi(struct irq_data *data) -{ - struct msi_desc *desc = irq_data_get_msi_desc(data); - - pci_msi_mask(desc, BIT(data->irq - desc->irq)); - cond_shutdown_parent(data); -} - -static unsigned int pci_irq_startup_msi(struct irq_data *data) -{ - struct msi_desc *desc = irq_data_get_msi_desc(data); - unsigned int ret = cond_startup_parent(data); - - pci_msi_unmask(desc, BIT(data->irq - desc->irq)); - return ret; -} - static void pci_irq_mask_msi(struct irq_data *data) { struct msi_desc *desc = irq_data_get_msi_desc(data); @@ -228,8 +194,6 @@ static void pci_irq_unmask_msi(struct irq_data *data) static const struct msi_domain_template pci_msi_template = { .chip = { .name = "PCI-MSI", - .irq_startup = pci_irq_startup_msi, - .irq_shutdown = pci_irq_shutdown_msi, .irq_mask = pci_irq_mask_msi, .irq_unmask = pci_irq_unmask_msi, .irq_write_msi_msg = pci_msi_domain_write_msg, @@ -246,20 +210,6 @@ static const struct msi_domain_template pci_msi_template = { }, }; -static void pci_irq_shutdown_msix(struct irq_data *data) -{ - pci_msix_mask(irq_data_get_msi_desc(data)); - cond_shutdown_parent(data); -} - -static unsigned int pci_irq_startup_msix(struct irq_data *data) -{ - unsigned int ret = cond_startup_parent(data); - - pci_msix_unmask(irq_data_get_msi_desc(data)); - return ret; -} - static void pci_irq_mask_msix(struct irq_data *data) { pci_msix_mask(irq_data_get_msi_desc(data)); @@ -284,8 +234,6 @@ EXPORT_SYMBOL_GPL(pci_msix_prepare_desc); static const struct msi_domain_template pci_msix_template = { .chip = { .name = "PCI-MSIX", - .irq_startup = pci_irq_startup_msix, - .irq_shutdown = pci_irq_shutdown_msix, .irq_mask = pci_irq_mask_msix, .irq_unmask = pci_irq_unmask_msix, .irq_write_msi_msg = pci_msi_domain_write_msg, diff --git a/include/linux/msi.h b/include/linux/msi.h index 3111ba95fbde49..e5e86a8529fb6f 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -568,8 +568,6 @@ enum { MSI_FLAG_PARENT_PM_DEV = (1 << 8), /* Support for parent mask/unmask */ MSI_FLAG_PCI_MSI_MASK_PARENT = (1 << 9), - /* Support for parent startup/shutdown */ - MSI_FLAG_PCI_MSI_STARTUP_PARENT = (1 << 10), /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), From b66db210123ea0d4a5a9f7b9be0bf5921134818b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:04 +0800 Subject: [PATCH 07/30] Revert "FROMLIST: genirq: Add irq_chip_(startup/shutdown)_parent()" This reverts commit e35a2195e2b2460c9da400b9d3abb5bccc00196f. --- include/linux/irq.h | 2 -- kernel/irq/chip.c | 37 ------------------------------------- 2 files changed, 39 deletions(-) diff --git a/include/linux/irq.h b/include/linux/irq.h index 890e1371f5d4c2..1d6b606a81efe5 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -669,8 +669,6 @@ extern int irq_chip_set_parent_state(struct irq_data *data, extern int irq_chip_get_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool *state); -extern void irq_chip_shutdown_parent(struct irq_data *data); -extern unsigned int irq_chip_startup_parent(struct irq_data *data); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 3ffa0d80ddd19c..0d0276378c707c 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1259,43 +1259,6 @@ int irq_chip_get_parent_state(struct irq_data *data, } EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); -/** - * irq_chip_shutdown_parent - Shutdown the parent interrupt - * @data: Pointer to interrupt specific data - * - * Invokes the irq_shutdown() callback of the parent if available or falls - * back to irq_chip_disable_parent(). - */ -void irq_chip_shutdown_parent(struct irq_data *data) -{ - struct irq_data *parent = data->parent_data; - - if (parent->chip->irq_shutdown) - parent->chip->irq_shutdown(parent); - else - irq_chip_disable_parent(data); -} -EXPORT_SYMBOL_GPL(irq_chip_shutdown_parent); - -/** - * irq_chip_startup_parent - Startup the parent interrupt - * @data: Pointer to interrupt specific data - * - * Invokes the irq_startup() callback of the parent if available or falls - * back to irq_chip_enable_parent(). - */ -unsigned int irq_chip_startup_parent(struct irq_data *data) -{ - struct irq_data *parent = data->parent_data; - - if (parent->chip->irq_startup) - return parent->chip->irq_startup(parent); - - irq_chip_enable_parent(data); - return 0; -} -EXPORT_SYMBOL_GPL(irq_chip_startup_parent); - /** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if * NULL) From 839c3d8ea3fccd0503e27b2a3ea294c936687dca Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:07 +0800 Subject: [PATCH 08/30] Revert "FROMLIST: irqchip/sifive-plic: Respect mask state when setting affinity" This reverts commit f8237b938f41944bce5e38ca2f3c8e5124798705. --- drivers/irqchip/irq-sifive-plic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 866e38612b948e..bf69a4802b71e7 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -179,14 +179,12 @@ static int plic_set_affinity(struct irq_data *d, if (cpu >= nr_cpu_ids) return -EINVAL; - /* Invalidate the original routing entry */ - plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); + plic_irq_disable(d); irq_data_update_effective_affinity(d, cpumask_of(cpu)); - /* Setting the new routing entry if irq is enabled */ if (!irqd_irq_disabled(d)) - plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); + plic_irq_enable(d); return IRQ_SET_MASK_OK_DONE; } From 0e12580b5b00974f64ca64ad644aede124b40694 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:12 +0800 Subject: [PATCH 09/30] Revert "FROMLIST: riscv: introduce ioremap_wc()" This reverts commit 855ac4613b9e26fcbf0177788377884548607cf7. --- arch/riscv/include/asm/io.h | 4 ---- arch/riscv/include/asm/pgtable.h | 1 - 2 files changed, 5 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 09bb5f57a9d346..a0e51840b9db43 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -28,10 +28,6 @@ #ifdef CONFIG_MMU #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) #define PCI_IOBASE ((void __iomem *)PCI_IO_START) - -#define ioremap_wc(addr, size) \ - ioremap_prot((addr), (size), __pgprot(_PAGE_KERNEL_NC)) - #endif /* CONFIG_MMU */ /* diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index a85d8800c1688a..81506774293980 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -203,7 +203,6 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_TABLE __pgprot(_PAGE_TABLE) -#define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) From e9f6c03c8dfb39053d06e2a6d3edc6f3d135962c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:14 +0800 Subject: [PATCH 10/30] Revert "FROMLIST: riscv: mmap(): use unsigned offset type in riscv_sys_mmap" This reverts commit f2f09f18267d35b20e59e9f8e6442cf3230ae143. --- arch/riscv/kernel/sys_riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 795b2e815ac923..d77afe05578f23 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -10,7 +10,7 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, - unsigned long fd, unsigned long offset, + unsigned long fd, off_t offset, unsigned long page_shift_offset) { if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) From 6c0062e80a338cdeb5558c94fa6306ab0f37b7de Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:50 +0800 Subject: [PATCH 11/30] Revert "FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver" This reverts commit ba538ba0e508a191d90207edf0ca17388594f69a. --- drivers/pci/controller/cadence/Kconfig | 10 -- drivers/pci/controller/cadence/Makefile | 1 - drivers/pci/controller/cadence/pcie-sg2042.c | 138 ------------------- 3 files changed, 149 deletions(-) delete mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 02a639e55fd8cf..666e16b6367f14 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,15 +42,6 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. -config PCIE_SG2042_HOST - tristate "Sophgo SG2042 PCIe controller (host mode)" - depends on OF && (ARCH_SOPHGO || COMPILE_TEST) - select PCIE_CADENCE_HOST - help - Say Y here if you want to support the Sophgo SG2042 PCIe platform - controller in host mode. Sophgo SG2042 PCIe controller uses Cadence - PCIe core. - config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST != n @@ -76,5 +67,4 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. - endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 5e23f8539ecc12..9bac5fb2f13dad 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,4 +4,3 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o -obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c deleted file mode 100644 index db91c37790b7dd..00000000000000 --- a/drivers/pci/controller/cadence/pcie-sg2042.c +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC - * - * Copyright (C) 2025 Sophgo Technology Inc. - * Copyright (C) 2025 Chen Wang - */ - -#include -#include -#include -#include - -#include "pcie-cadence.h" - -/* - * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to - * read/write the Root Port itself, read32/write32 is required. For - * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports - * 1/2/4 byte aligned access, so directly using read/write should be fine. - */ - -static struct pci_ops sg2042_pcie_root_ops = { - .map_bus = cdns_pci_map_bus, - .read = pci_generic_config_read32, - .write = pci_generic_config_write32, -}; - -static struct pci_ops sg2042_pcie_child_ops = { - .map_bus = cdns_pci_map_bus, - .read = pci_generic_config_read, - .write = pci_generic_config_write, -}; - -static int sg2042_pcie_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct pci_host_bridge *bridge; - struct cdns_pcie *pcie; - struct cdns_pcie_rc *rc; - int ret; - - bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); - if (!bridge) { - dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n"); - return -ENOMEM; - } - - bridge->ops = &sg2042_pcie_root_ops; - bridge->child_ops = &sg2042_pcie_child_ops; - - rc = pci_host_bridge_priv(bridge); - pcie = &rc->pcie; - pcie->dev = dev; - - platform_set_drvdata(pdev, pcie); - - pm_runtime_set_active(dev); - pm_runtime_no_callbacks(dev); - devm_pm_runtime_enable(dev); - - ret = cdns_pcie_init_phy(dev, pcie); - if (ret) { - dev_err_probe(dev, ret, "Failed to init phy!\n"); - return ret; - } - - ret = cdns_pcie_host_setup(rc); - if (ret) { - dev_err_probe(dev, ret, "Failed to setup host!\n"); - cdns_pcie_disable_phy(pcie); - return ret; - } - - return 0; -} - -static void sg2042_pcie_remove(struct platform_device *pdev) -{ - struct cdns_pcie *pcie = platform_get_drvdata(pdev); - struct device *dev = &pdev->dev; - struct cdns_pcie_rc *rc; - - rc = container_of(pcie, struct cdns_pcie_rc, pcie); - cdns_pcie_host_disable(rc); - - cdns_pcie_disable_phy(pcie); - - pm_runtime_disable(dev); -} - -static int sg2042_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie = dev_get_drvdata(dev); - - cdns_pcie_disable_phy(pcie); - - return 0; -} - -static int sg2042_pcie_resume_noirq(struct device *dev) -{ - struct cdns_pcie *pcie = dev_get_drvdata(dev); - int ret; - - ret = cdns_pcie_enable_phy(pcie); - if (ret) { - dev_err(dev, "failed to enable PHY\n"); - return ret; - } - - return 0; -} - -static DEFINE_NOIRQ_DEV_PM_OPS(sg2042_pcie_pm_ops, - sg2042_pcie_suspend_noirq, - sg2042_pcie_resume_noirq); - -static const struct of_device_id sg2042_pcie_of_match[] = { - { .compatible = "sophgo,sg2042-pcie-host" }, - {}, -}; -MODULE_DEVICE_TABLE(of, sg2042_pcie_of_match); - -static struct platform_driver sg2042_pcie_driver = { - .driver = { - .name = "sg2042-pcie", - .of_match_table = sg2042_pcie_of_match, - .pm = pm_sleep_ptr(&sg2042_pcie_pm_ops), - }, - .probe = sg2042_pcie_probe, - .remove = sg2042_pcie_remove, -}; -module_platform_driver(sg2042_pcie_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs"); -MODULE_AUTHOR("Chen Wang "); From affbe6a099040b7f1e67ea02d3b83a7d616f1d75 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:53 +0800 Subject: [PATCH 12/30] Revert "FROMLIST: PCI: cadence: Check pcie-ops before using it" This reverts commit d0253a4c82885fe2fe7b553ef6d8ee5892a0759c. --- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index fffd63d6665e81..59a4631de79fe8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 61806bbd8aa326..70a19573440ee9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | @@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, } /* Set the CPU address */ - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 2f07ba661bda78..1d81c4bf6c6db7 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -468,7 +468,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->start_link) + if (pcie->ops->start_link) return pcie->ops->start_link(pcie); return 0; @@ -476,13 +476,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->stop_link) + if (pcie->ops->stop_link) pcie->ops->stop_link(pcie); } static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->link_up) + if (pcie->ops->link_up) return pcie->ops->link_up(pcie); return true; From c86037a8d42043a759fd56db6527b620032c72de Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:56 +0800 Subject: [PATCH 13/30] Revert "FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host" This reverts commit 6060c57a10ce2a3359aaa6fe37461a8e9ca617f9. --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ------------------- 1 file changed, 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml deleted file mode 100644 index f8b7ca57fff14c..00000000000000 --- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) - -description: - Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. - -maintainers: - - Chen Wang - -properties: - compatible: - const: sophgo,sg2042-pcie-host - - reg: - maxItems: 2 - - reg-names: - items: - - const: reg - - const: cfg - - vendor-id: - const: 0x1f1c - - device-id: - const: 0x2042 - - msi-parent: true - -allOf: - - $ref: cdns-pcie-host.yaml# - -required: - - compatible - - reg - - reg-names - -unevaluatedProperties: false - -examples: - - | - #include - - pcie@62000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x62000000 0x00800000>, - <0x48000000 0x00001000>; - reg-names = "reg", "cfg"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, - <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - bus-range = <0x00 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - }; From 542c906336112cd0c67c0e9aa775c46daf19ff06 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 10 Oct 2025 08:51:58 +0800 Subject: [PATCH 14/30] Revert "FROMLIST: dts: sophgo: sg2042: added numa id description" This reverts commit cc9899650998d620616930f1185d3b7025fded48. --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 64 --------------------- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 20 ------- 2 files changed, 84 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 94a4b71acad320..77ded530427282 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -272,7 +272,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -300,7 +299,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -328,7 +326,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -356,7 +353,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -384,7 +380,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -412,7 +407,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu5_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -440,7 +434,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu6_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -468,7 +461,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu7_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -496,7 +488,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu8_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -524,7 +515,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu9_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -552,7 +542,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu10_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -580,7 +569,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu11_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -608,7 +596,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu12_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -636,7 +623,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu13_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -664,7 +650,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu14_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -692,7 +677,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu15_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -720,7 +704,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu16_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -748,7 +731,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu17_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -776,7 +758,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu18_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -804,7 +785,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu19_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -832,7 +812,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu20_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -860,7 +839,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu21_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -888,7 +866,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu22_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -916,7 +893,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; - numa-node-id = <0>; cpu23_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -944,7 +920,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu24_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -972,7 +947,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu25_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1000,7 +974,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu26_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1028,7 +1001,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu27_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1056,7 +1028,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu28_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1084,7 +1055,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu29_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1112,7 +1082,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu30_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1140,7 +1109,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; - numa-node-id = <1>; cpu31_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1168,7 +1136,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu32_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1196,7 +1163,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu33_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1224,7 +1190,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu34_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1252,7 +1217,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu35_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1280,7 +1244,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu36_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1308,7 +1271,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu37_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1336,7 +1298,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu38_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1364,7 +1325,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu39_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1392,7 +1352,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu40_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1420,7 +1379,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu41_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1448,7 +1406,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu42_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1476,7 +1433,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu43_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1504,7 +1460,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu44_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1532,7 +1487,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu45_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1560,7 +1514,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu46_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1588,7 +1541,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu47_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1616,7 +1568,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu48_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1644,7 +1595,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu49_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1672,7 +1622,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu50_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1700,7 +1649,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu51_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1728,7 +1676,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu52_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1756,7 +1703,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu53_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1784,7 +1730,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu54_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1812,7 +1757,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; - numa-node-id = <2>; cpu55_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1840,7 +1784,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu56_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1868,7 +1811,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu57_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1896,7 +1838,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu58_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1924,7 +1865,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu59_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1952,7 +1892,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu60_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1980,7 +1919,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu61_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -2008,7 +1946,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu62_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -2036,7 +1973,6 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; - numa-node-id = <3>; cpu63_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index caad6117845c13..a8e509495d1f78 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -19,26 +19,6 @@ #size-cells = <2>; dma-noncoherent; - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 15>, - <0 2 25>, - <0 3 30>, - <1 0 15>, - <1 1 10>, - <1 2 30>, - <1 3 25>, - <2 0 25>, - <2 1 30>, - <2 2 10>, - <2 3 15>, - <3 0 30>, - <3 1 25>, - <3 2 15>, - <3 3 10>; - }; - aliases { serial0 = &uart0; }; From 1bffa00a05760cfbc8a266781ffb13dbaac38a91 Mon Sep 17 00:00:00 2001 From: Jessica Liu Date: Fri, 1 Aug 2025 10:49:48 +0800 Subject: [PATCH 15/30] UPSTREAM: riscv: mmap(): use unsigned offset type in riscv_sys_mmap The variable type of offset should be consistent with the relevant interfaces of mmap which described in commit 295f10061af0 ("syscalls: mmap(): use unsigned offset type consistently"). Otherwise, a user input with the top bit set would result in a negative page offset rather than a large one. Signed-off-by: Jessica Liu Tested-by: Han Gao Reviewed-by: Alexandre Ghiti Reviewed-by: Nutty Liu Link: https://lore.kernel.org/r/20250801104948133AaMr5S6E382PbNNhoJgHA@zte.com.cn [pjw@kernel.org: hand-applied mangled patch; fixed checkpatch error] Signed-off-by: Paul Walmsley (cherry picked from commit 316b60b984d5be9b86047cdf3bf16d51c7c70cc5) Signed-off-by: Han Gao --- arch/riscv/kernel/sys_riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index d77afe05578f23..795b2e815ac923 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -10,7 +10,7 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, - unsigned long fd, off_t offset, + unsigned long fd, unsigned long offset, unsigned long page_shift_offset) { if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) From c85dfb23bd623d83b035d0c569b51d7a4af13354 Mon Sep 17 00:00:00 2001 From: Yunhui Cui Date: Tue, 22 Jul 2025 17:15:04 +0800 Subject: [PATCH 16/30] UPSTREAM: riscv: introduce ioremap_wc() Compared with IO attributes, NC attributes can improve performance, specifically in these aspects: Relaxed Order, Gathering, Supports Read Speculation, Supports Unaligned Access. Signed-off-by: Yunhui Cui Signed-off-by: Qingfang Deng Reviewed-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20250722091504.45974-2-cuiyunhui@bytedance.com Signed-off-by: Paul Walmsley (cherry picked from commit 3a8ee3a9f4f6caca192fd2fdc88c1ce56c521b38) Signed-off-by: Han Gao --- arch/riscv/include/asm/io.h | 4 ++++ arch/riscv/include/asm/pgtable.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index a0e51840b9db43..09bb5f57a9d346 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -28,6 +28,10 @@ #ifdef CONFIG_MMU #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) #define PCI_IOBASE ((void __iomem *)PCI_IO_START) + +#define ioremap_wc(addr, size) \ + ioremap_prot((addr), (size), __pgprot(_PAGE_KERNEL_NC)) + #endif /* CONFIG_MMU */ /* diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 81506774293980..a85d8800c1688a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -203,6 +203,7 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_TABLE __pgprot(_PAGE_TABLE) +#define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) From 659bb3979e3951b8eb8531b08d63928300852cb9 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 11 Aug 2025 08:26:32 +0800 Subject: [PATCH 17/30] UPSTREAM: irqchip/sifive-plic: Respect mask state when setting affinity plic_set_affinity() always calls plic_irq_enable(), which clears up the priority setting even the interrupt is only masked. This unmasks the interrupt unexpectly. Replace the plic_irq_enable/disable() with plic_irq_toggle() to avoid changing the priority setting. Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Nam Cao # VisionFive 2 Tested-by: Chen Wang # Pioneerbox Reviewed-by: Nam Cao Reviewed-by: Chen Wang Link: https://lore.kernel.org/all/20250811002633.55275-1-inochiama@gmail.com Link: https://lore.kernel.org/lkml/20250722224513.22125-1-inochiama@gmail.com/ (cherry picked from commit adecf78df945f4c7a1d29111b0002827f487df51) Signed-off-by: Han Gao --- drivers/irqchip/irq-sifive-plic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bf69a4802b71e7..866e38612b948e 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -179,12 +179,14 @@ static int plic_set_affinity(struct irq_data *d, if (cpu >= nr_cpu_ids) return -EINVAL; - plic_irq_disable(d); + /* Invalidate the original routing entry */ + plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); irq_data_update_effective_affinity(d, cpumask_of(cpu)); + /* Setting the new routing entry if irq is enabled */ if (!irqd_irq_disabled(d)) - plic_irq_enable(d); + plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); return IRQ_SET_MASK_OK_DONE; } From 896da842558c9cf9c0ebead4f53b94f60f9c941a Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 14 Aug 2025 07:28:31 +0800 Subject: [PATCH 18/30] UPSTREAM: genirq: Add irq_chip_(startup/shutdown)_parent() As the MSI controller on SG2044 uses PLIC as the underlying interrupt controller, it needs to call irq_enable() and irq_disable() to startup/shutdown interrupts. Otherwise, the MSI interrupt can not be startup correctly and will not respond any incoming interrupt. Introduce irq_chip_startup_parent() and irq_chip_shutdown_parent() to allow the interrupt controller to call the irq_startup()/irq_shutdown() callbacks of the parent interrupt chip. In case the irq_startup()/irq_shutdown() callbacks are not implemented for the parent interrupt chip, this will fallback to irq_chip_enable_parent() or irq_chip_disable_parent(). Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Chen Wang # Pioneerbox Reviewed-by: Chen Wang Link: https://lore.kernel.org/all/20250813232835.43458-2-inochiama@gmail.com Link: https://lore.kernel.org/lkml/20250722224513.22125-1-inochiama@gmail.com/ (cherry picked from commit 7a721a2fee2bce01af26699a87739db8ca8ea3c8) Signed-off-by: Han Gao --- include/linux/irq.h | 2 ++ kernel/irq/chip.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 1d6b606a81efe5..890e1371f5d4c2 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -669,6 +669,8 @@ extern int irq_chip_set_parent_state(struct irq_data *data, extern int irq_chip_get_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool *state); +extern void irq_chip_shutdown_parent(struct irq_data *data); +extern unsigned int irq_chip_startup_parent(struct irq_data *data); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 0d0276378c707c..3ffa0d80ddd19c 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1259,6 +1259,43 @@ int irq_chip_get_parent_state(struct irq_data *data, } EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); +/** + * irq_chip_shutdown_parent - Shutdown the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_shutdown() callback of the parent if available or falls + * back to irq_chip_disable_parent(). + */ +void irq_chip_shutdown_parent(struct irq_data *data) +{ + struct irq_data *parent = data->parent_data; + + if (parent->chip->irq_shutdown) + parent->chip->irq_shutdown(parent); + else + irq_chip_disable_parent(data); +} +EXPORT_SYMBOL_GPL(irq_chip_shutdown_parent); + +/** + * irq_chip_startup_parent - Startup the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_startup() callback of the parent if available or falls + * back to irq_chip_enable_parent(). + */ +unsigned int irq_chip_startup_parent(struct irq_data *data) +{ + struct irq_data *parent = data->parent_data; + + if (parent->chip->irq_startup) + return parent->chip->irq_startup(parent); + + irq_chip_enable_parent(data); + return 0; +} +EXPORT_SYMBOL_GPL(irq_chip_startup_parent); + /** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if * NULL) From ce12d82825393393983f78cd50deb916c3412498 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 14 Aug 2025 07:28:32 +0800 Subject: [PATCH 19/30] UPSTREAM: PCI/MSI: Add startup/shutdown for per device domains As the RISC-V PLIC cannot apply affinity settings without invoking irq_enable(), it will make the interrupt unavailble when used as an underlying interrupt chip for the MSI controller. Implement the irq_startup() and irq_shutdown() callbacks for the PCI MSI and MSI-X templates. For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, the parent startup and shutdown functions are invoked. That allows the interrupt on the parent chip to be enabled if the interrupt has not been enabled during allocation. This is necessary for MSI controllers which use PLIC as underlying parent interrupt chip. Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Chen Wang # Pioneerbox Reviewed-by: Chen Wang Acked-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20250813232835.43458-3-inochiama@gmail.com (cherry picked from commit 54f45a30c0d0153d2be091ba2d683ab6db6d1d5b) Signed-off-by: Han Gao --- drivers/pci/msi/irqdomain.c | 52 +++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index 0938ef7ebabf2d..e0a800f918e812 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -148,6 +148,23 @@ static void pci_device_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *d arg->hwirq = desc->msi_index; } +static void cond_shutdown_parent(struct irq_data *data) +{ + struct msi_domain_info *info = data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + irq_chip_shutdown_parent(data); +} + +static unsigned int cond_startup_parent(struct irq_data *data) +{ + struct msi_domain_info *info = data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + return irq_chip_startup_parent(data); + return 0; +} + static __always_inline void cond_mask_parent(struct irq_data *data) { struct msi_domain_info *info = data->domain->host_data; @@ -164,6 +181,23 @@ static __always_inline void cond_unmask_parent(struct irq_data *data) irq_chip_unmask_parent(data); } +static void pci_irq_shutdown_msi(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + + pci_msi_mask(desc, BIT(data->irq - desc->irq)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msi(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + unsigned int ret = cond_startup_parent(data); + + pci_msi_unmask(desc, BIT(data->irq - desc->irq)); + return ret; +} + static void pci_irq_mask_msi(struct irq_data *data) { struct msi_desc *desc = irq_data_get_msi_desc(data); @@ -194,6 +228,8 @@ static void pci_irq_unmask_msi(struct irq_data *data) static const struct msi_domain_template pci_msi_template = { .chip = { .name = "PCI-MSI", + .irq_startup = pci_irq_startup_msi, + .irq_shutdown = pci_irq_shutdown_msi, .irq_mask = pci_irq_mask_msi, .irq_unmask = pci_irq_unmask_msi, .irq_write_msi_msg = pci_msi_domain_write_msg, @@ -210,6 +246,20 @@ static const struct msi_domain_template pci_msi_template = { }, }; +static void pci_irq_shutdown_msix(struct irq_data *data) +{ + pci_msix_mask(irq_data_get_msi_desc(data)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msix(struct irq_data *data) +{ + unsigned int ret = cond_startup_parent(data); + + pci_msix_unmask(irq_data_get_msi_desc(data)); + return ret; +} + static void pci_irq_mask_msix(struct irq_data *data) { pci_msix_mask(irq_data_get_msi_desc(data)); @@ -234,6 +284,8 @@ EXPORT_SYMBOL_GPL(pci_msix_prepare_desc); static const struct msi_domain_template pci_msix_template = { .chip = { .name = "PCI-MSIX", + .irq_startup = pci_irq_startup_msix, + .irq_shutdown = pci_irq_shutdown_msix, .irq_mask = pci_irq_mask_msix, .irq_unmask = pci_irq_unmask_msix, .irq_write_msi_msg = pci_msi_domain_write_msg, diff --git a/include/linux/msi.h b/include/linux/msi.h index e5e86a8529fb6f..3111ba95fbde49 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -568,6 +568,8 @@ enum { MSI_FLAG_PARENT_PM_DEV = (1 << 8), /* Support for parent mask/unmask */ MSI_FLAG_PCI_MSI_MASK_PARENT = (1 << 9), + /* Support for parent startup/shutdown */ + MSI_FLAG_PCI_MSI_STARTUP_PARENT = (1 << 10), /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), From 8b12d1b74e00295325243bc7338f964b2f278f24 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 14 Aug 2025 07:28:33 +0800 Subject: [PATCH 20/30] UPSTREAM: irqchip/sg2042-msi: Fix broken affinity setting When using NVME on SG2044, the NVME drvier always complains about "I/O tag XXX (XXX) QID XX timeout, completion polled", which is caused by the broken affinity setting mechanism of the sg2042-msi driver. The PLIC driver can only the set the affinity when enabled, but the sg2042-msi driver invokes the affinity setter in disabled state, which causes the change to be lost. Cure this by implementing the irq_startup()/shutdown() callbacks, which allow to startup (enabled) the underlying PLIC first. Fixes: e96b93a97c90 ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller") Reported-by: Han Gao Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Chen Wang # Pioneerbox Reviewed-by: Chen Wang Link: https://lore.kernel.org/all/20250813232835.43458-4-inochiama@gmail.com (cherry picked from commit 9d8c41816bac518b4824f83b346ae30a1be83f68) Signed-off-by: Han Gao --- drivers/irqchip/irq-sg2042-msi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-msi.c index bcfddc51bc6a18..2fd4d94f9bd76d 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -85,6 +85,8 @@ static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *m static const struct irq_chip sg2042_msi_middle_irq_chip = { .name = "SG2042 MSI", + .irq_startup = irq_chip_startup_parent, + .irq_shutdown = irq_chip_shutdown_parent, .irq_ack = sg2042_msi_irq_ack, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, @@ -114,6 +116,8 @@ static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *m static struct irq_chip sg2044_msi_middle_irq_chip = { .name = "SG2044 MSI", + .irq_startup = irq_chip_startup_parent, + .irq_shutdown = irq_chip_shutdown_parent, .irq_ack = sg2044_msi_irq_ack, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, @@ -185,8 +189,10 @@ static const struct irq_domain_ops sg204x_msi_middle_domain_ops = { .select = msi_lib_irq_domain_select, }; -#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK @@ -200,10 +206,12 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = { .init_dev_msi_info = msi_lib_init_dev_msi_info, }; -#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) -#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ MSI_FLAG_PCI_MSIX) static const struct msi_parent_ops sg2044_msi_parent_ops = { From f8448fbc4123eae168c63854afb0626cf89a4275 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 14 Aug 2025 07:28:34 +0800 Subject: [PATCH 21/30] UPSTREAM: irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flags for SG2044 The MSI controller on SG2044 has the ability to allocate multiple PCI MSI interrupts. So the PCIe controller driver can use this feature if the hardware supports multiple PCI MSI interrupts. Add the MSI_FLAG_MULTI_PCI_MSI flag to the supported_flags of SG2044 msi_parent_ops to enable this functionality. Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Chen Wang # Pioneerbox Reviewed-by: Chen Wang Link: https://lore.kernel.org/all/20250813232835.43458-5-inochiama@gmail.com (cherry picked from commit 7ee4a5a2ec3748facfb4ca96e4cce6cabbdecab2) Signed-off-by: Han Gao --- drivers/irqchip/irq-sg2042-msi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-msi.c index 2fd4d94f9bd76d..3b13dbbfdb51c0 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -212,6 +212,7 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = { MSI_FLAG_PCI_MSI_STARTUP_PARENT) #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX) static const struct msi_parent_ops sg2044_msi_parent_ops = { From 35a3900401b7f6436740982bc02b73eba01c8ab7 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 28 Aug 2025 07:09:42 +0800 Subject: [PATCH 22/30] UPSTREAM: PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent() For MSI controllers which only support MSI_FLAG_PCI_MSI_MASK_PARENT, the newly added callback irq_startup() and irq_shutdown() for pci_msi[x]_template will not unmask or mask the interrupt when startup() resp. shutdown() is invoked. This prevents the interrupt from being enabled resp. disabled. Invoke irq_[un]mask_parent() in cond_[startup|shutdown]_parent(), when the interrupt has the MSI_FLAG_PCI_MSI_MASK_PARENT flag set. Fixes: 54f45a30c0d0 ("PCI/MSI: Add startup/shutdown for per device domains") Reported-by: Linux Kernel Functional Testing Reported-by: Nathan Chancellor Reported-by: Wei Fang Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Tested-by: Nathan Chancellor Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Wei Fang Tested-by: Chen Wang # Pioneerbox/SG2042 Acked-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20250827230943.17829-1-inochiama@gmail.com Closes: https://lore.kernel.org/regressions/aK4O7Hl8NCVEMznB@monster/ Closes: https://lore.kernel.org/regressions/20250826220959.GA4119563@ax162/ Closes: https://lore.kernel.org/all/20250827093911.1218640-1-wei.fang@nxp.com/ (cherry picked from commit 727e914bbfbbda9e6efa5cb1abe4e96a949d576f) Signed-off-by: Han Gao --- drivers/pci/msi/irqdomain.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index e0a800f918e812..b11b7f63f0d6fc 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -154,6 +154,8 @@ static void cond_shutdown_parent(struct irq_data *data) if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) irq_chip_shutdown_parent(data); + else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT)) + irq_chip_mask_parent(data); } static unsigned int cond_startup_parent(struct irq_data *data) @@ -162,6 +164,9 @@ static unsigned int cond_startup_parent(struct irq_data *data) if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) return irq_chip_startup_parent(data); + else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT)) + irq_chip_unmask_parent(data); + return 0; } From 373fc8db873c8777e9da234c65b20c98d82cacad Mon Sep 17 00:00:00 2001 From: "Guo Ren (Alibaba DAMO Academy)" Date: Sun, 13 Jul 2025 11:53:20 -0400 Subject: [PATCH 23/30] UPSTREAM: riscv: Move vendor errata definitions to new header Move vendor errata definitions into errata_list_vendors.h. Signed-off-by: Guo Ren (Alibaba DAMO Academy) Reviewed-by: Alexandre Ghiti Tested-by: Han Gao Link: https://lore.kernel.org/r/20250713155321.2064856-2-guoren@kernel.org [pjw@kernel.org: updated to apply and to make the whitespace consistent] Signed-off-by: Paul Walmsley (cherry picked from commit 16d18e3eaf29be1d987f5238ec03226f15dad5f5) Signed-off-by: Han Gao --- arch/riscv/include/asm/errata_list.h | 19 +--------------- arch/riscv/include/asm/errata_list_vendors.h | 24 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/include/asm/errata_list_vendors.h diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 6e426ed7919a4a..18c9f7ee9b7c45 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -10,24 +10,7 @@ #include #include #include - -#ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDES_NO_IOCP 0 -#define ERRATA_ANDES_NUMBER 1 -#endif - -#ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 -#endif - -#ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_MAE 0 -#define ERRATA_THEAD_PMU 1 -#define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 -#endif +#include #ifdef __ASSEMBLY__ diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h new file mode 100644 index 00000000000000..d448b9ce7c7c58 --- /dev/null +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM_ERRATA_LIST_VENDORS_H +#define ASM_ERRATA_LIST_VENDORS_H + +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 +#endif + +#ifdef CONFIG_ERRATA_SIFIVE +#define ERRATA_SIFIVE_CIP_453 0 +#define ERRATA_SIFIVE_CIP_1200 1 +#define ERRATA_SIFIVE_NUMBER 2 +#endif + +#ifdef CONFIG_ERRATA_THEAD +#define ERRATA_THEAD_MAE 0 +#define ERRATA_THEAD_PMU 1 +#define ERRATA_THEAD_GHOSTWRITE 2 +#define ERRATA_THEAD_NUMBER 3 +#endif + +#endif /* ASM_ERRATA_LIST_VENDORS_H */ From db4ef7f0cc967cbf9a7651124eeb922051b62970 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 10 Sep 2025 18:55:31 +0800 Subject: [PATCH 24/30] UPSTREAM: dts: sophgo: sg2042: added numa id description According to the description of [1], sg2042 is divided into 4 numa. STREAM test performance will improve. Before: Function Best Rate MB/s Avg time Min time Max time Copy: 10739.7 0.015687 0.014898 0.016385 Scale: 10865.9 0.015628 0.014725 0.016757 Add: 10622.3 0.023276 0.022594 0.023899 Triad: 10583.4 0.023653 0.022677 0.024761 After: Function Best Rate MB/s Avg time Min time Max time Copy: 34254.9 0.005142 0.004671 0.005995 Scale: 37735.5 0.004752 0.004240 0.005407 Add: 44206.8 0.005983 0.005429 0.006461 Triad: 43040.6 0.006320 0.005576 0.006996 [1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png Signed-off-by: Han Gao Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250910105531.519897-1-rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang (cherry picked from commit 4d94abded400a5194b929c26b3aa07fb9485fe35) Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 64 +++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 20 +++++++ 2 files changed, 84 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 77ded530427282..94a4b71acad320 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -272,6 +272,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -299,6 +300,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -326,6 +328,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -353,6 +356,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -380,6 +384,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -407,6 +412,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu5_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -434,6 +440,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu6_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -461,6 +468,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu7_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -488,6 +496,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu8_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -515,6 +524,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu9_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -542,6 +552,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu10_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -569,6 +580,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu11_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -596,6 +608,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu12_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -623,6 +636,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu13_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -650,6 +664,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu14_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -677,6 +692,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu15_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -704,6 +720,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu16_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -731,6 +748,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu17_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -758,6 +776,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu18_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -785,6 +804,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu19_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -812,6 +832,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu20_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -839,6 +860,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu21_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -866,6 +888,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu22_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -893,6 +916,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu23_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -920,6 +944,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu24_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -947,6 +972,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu25_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -974,6 +1000,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu26_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1001,6 +1028,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu27_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1028,6 +1056,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu28_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1055,6 +1084,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu29_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1082,6 +1112,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu30_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1109,6 +1140,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu31_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1136,6 +1168,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu32_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1163,6 +1196,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu33_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1190,6 +1224,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu34_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1217,6 +1252,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu35_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1244,6 +1280,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu36_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1271,6 +1308,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu37_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1298,6 +1336,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu38_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1325,6 +1364,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu39_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1352,6 +1392,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu40_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1379,6 +1420,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu41_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1406,6 +1448,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu42_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1433,6 +1476,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu43_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1460,6 +1504,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu44_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1487,6 +1532,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu45_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1514,6 +1560,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu46_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1541,6 +1588,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu47_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1568,6 +1616,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu48_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1595,6 +1644,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu49_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1622,6 +1672,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu50_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1649,6 +1700,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu51_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1676,6 +1728,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu52_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1703,6 +1756,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu53_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1730,6 +1784,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu54_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1757,6 +1812,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu55_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1784,6 +1840,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu56_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1811,6 +1868,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu57_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1838,6 +1896,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu58_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1865,6 +1924,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu59_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1892,6 +1952,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu60_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1919,6 +1980,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu61_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1946,6 +2008,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu62_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1973,6 +2036,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu63_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index a8e509495d1f78..caad6117845c13 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -19,6 +19,26 @@ #size-cells = <2>; dma-noncoherent; + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 25>, + <0 3 30>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>; + }; + aliases { serial0 = &uart0; }; From f8d3da29769299f085a32a1703ed0168f0142fd6 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:35:32 +0800 Subject: [PATCH 25/30] UPSTREAM: dt-bindings: pci: Add Sophgo SG2042 PCIe host Add binding for Sophgo SG2042 PCIe host controller. Signed-off-by: Chen Wang Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 4e4a4f58bed19e1a3a5a7c3a18ce3b927b76fcd3) Signed-off-by: Han Gao --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file mode 100644 index 00000000000000..f8b7ca57fff14c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + msi-parent: true + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x00 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + }; From 4c28c2efed199b9197d11b5538d57d76d5b97fd8 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:36:01 +0800 Subject: [PATCH 26/30] UPSTREAM: PCI: cadence: Check for the existence of cdns_pcie::ops before using it cdns_pcie::ops might not be populated by all the Cadence glue drivers. This is going to be true for the upcoming Sophgo platform which doesn't set the ops. Hence, add a check to prevent NULL pointer dereference. Signed-off-by: Chen Wang [mani: reworded subject and description] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 49a6c160ad4812476f8ae1a8f4ed6d15adfa6c09) Signed-off-by: Han Gao --- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 59a4631de79fe8..fffd63d6665e81 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 70a19573440ee9..61806bbd8aa326 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | @@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, } /* Set the CPU address */ - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 1d81c4bf6c6db7..2f07ba661bda78 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -468,7 +468,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) { - if (pcie->ops->start_link) + if (pcie->ops && pcie->ops->start_link) return pcie->ops->start_link(pcie); return 0; @@ -476,13 +476,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) { - if (pcie->ops->stop_link) + if (pcie->ops && pcie->ops->stop_link) pcie->ops->stop_link(pcie); } static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) { - if (pcie->ops->link_up) + if (pcie->ops && pcie->ops->link_up) return pcie->ops->link_up(pcie); return true; From fc7ca56b7c3feb11dd7585fac58810e921635710 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:36:31 +0800 Subject: [PATCH 27/30] UPSTREAM: PCI: sg2042: Add Sophgo SG2042 PCIe driver Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 1c72774df028429836eec3394212f2921bb830fc) Signed-off-by: Han Gao --- drivers/pci/controller/cadence/Kconfig | 10 ++ drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 134 +++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 666e16b6367f14..02a639e55fd8cf 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,6 +42,15 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCIE_SG2042_HOST + tristate "Sophgo SG2042 PCIe controller (host mode)" + depends on OF && (ARCH_SOPHGO || COMPILE_TEST) + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the Sophgo SG2042 PCIe platform + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence + PCIe core. + config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST != n @@ -67,4 +76,5 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 9bac5fb2f13dad..5e23f8539ecc12 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c new file mode 100644 index 00000000000000..a077b28d489494 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-sg2042.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC + * + * Copyright (C) 2025 Sophgo Technology Inc. + * Copyright (C) 2025 Chen Wang + */ + +#include +#include +#include +#include + +#include "pcie-cadence.h" + +/* + * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to + * read/write the Root Port itself, read32/write32 is required. For + * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports + * 1/2/4 byte aligned access, so directly using read/write should be fine. + */ + +static struct pci_ops sg2042_pcie_root_ops = { + .map_bus = cdns_pci_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, +}; + +static struct pci_ops sg2042_pcie_child_ops = { + .map_bus = cdns_pci_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +static int sg2042_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *pcie; + struct cdns_pcie_rc *rc; + int ret; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n"); + + bridge->ops = &sg2042_pcie_root_ops; + bridge->child_ops = &sg2042_pcie_child_ops; + + rc = pci_host_bridge_priv(bridge); + pcie = &rc->pcie; + pcie->dev = dev; + + platform_set_drvdata(pdev, pcie); + + pm_runtime_set_active(dev); + pm_runtime_no_callbacks(dev); + devm_pm_runtime_enable(dev); + + ret = cdns_pcie_init_phy(dev, pcie); + if (ret) + return dev_err_probe(dev, ret, "Failed to init phy!\n"); + + ret = cdns_pcie_host_setup(rc); + if (ret) { + dev_err_probe(dev, ret, "Failed to setup host!\n"); + cdns_pcie_disable_phy(pcie); + return ret; + } + + return 0; +} + +static void sg2042_pcie_remove(struct platform_device *pdev) +{ + struct cdns_pcie *pcie = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct cdns_pcie_rc *rc; + + rc = container_of(pcie, struct cdns_pcie_rc, pcie); + cdns_pcie_host_disable(rc); + + cdns_pcie_disable_phy(pcie); + + pm_runtime_disable(dev); +} + +static int sg2042_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int sg2042_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(sg2042_pcie_pm_ops, + sg2042_pcie_suspend_noirq, + sg2042_pcie_resume_noirq); + +static const struct of_device_id sg2042_pcie_of_match[] = { + { .compatible = "sophgo,sg2042-pcie-host" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sg2042_pcie_of_match); + +static struct platform_driver sg2042_pcie_driver = { + .driver = { + .name = "sg2042-pcie", + .of_match_table = sg2042_pcie_of_match, + .pm = pm_sleep_ptr(&sg2042_pcie_pm_ops), + }, + .probe = sg2042_pcie_probe, + .remove = sg2042_pcie_remove, +}; +module_platform_driver(sg2042_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs"); +MODULE_AUTHOR("Chen Wang "); From 49d801c45a3e7a4324b6cb70629b50eeba62309f Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 22 Jul 2025 00:53:10 +0800 Subject: [PATCH 28/30] UPSTREAM: riscv: mm: Return intended SATP mode for noXlvl options Change the return value of match_noXlvl() to return the SATP mode that will be used, rather than the mode being disabled. This enables unified logic for return value judgement with the function that obtains mmu-type from the fdt, avoiding extra conversion. This only changes the naming, with no functional impact. Signed-off-by: Junhui Liu Reviewed-by: Alexandre Ghiti Reviewed-by: Nutty Liu Link: https://lore.kernel.org/r/20250722-satp-from-fdt-v1-1-5ba22218fa5f@pigmoral.tech Signed-off-by: Paul Walmsley (cherry picked from commit f3243bed39c26ce0f13e6392a634f91d409b2d02) Signed-off-by: Han Gao --- arch/riscv/kernel/pi/cmdline_early.c | 4 ++-- arch/riscv/mm/init.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/pi/cmdline_early.c b/arch/riscv/kernel/pi/cmdline_early.c index fbcdc9e4e14322..389d086a071876 100644 --- a/arch/riscv/kernel/pi/cmdline_early.c +++ b/arch/riscv/kernel/pi/cmdline_early.c @@ -41,9 +41,9 @@ static char *get_early_cmdline(uintptr_t dtb_pa) static u64 match_noXlvl(char *cmdline) { if (strstr(cmdline, "no4lvl")) - return SATP_MODE_48; + return SATP_MODE_39; else if (strstr(cmdline, "no5lvl")) - return SATP_MODE_57; + return SATP_MODE_48; return 0; } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 15683ae13fa5d1..054265b3f26803 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -864,9 +864,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) kernel_map.page_offset = PAGE_OFFSET_L5; - if (satp_mode_cmdline == SATP_MODE_57) { + if (satp_mode_cmdline == SATP_MODE_48) { disable_pgtable_l5(); - } else if (satp_mode_cmdline == SATP_MODE_48) { + } else if (satp_mode_cmdline == SATP_MODE_39) { disable_pgtable_l5(); disable_pgtable_l4(); return; From e586c9f573aeca1f23b0d976bdfc040879e4655f Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 22 Jul 2025 00:53:11 +0800 Subject: [PATCH 29/30] UPSTREAM: riscv: mm: Use mmu-type from FDT to limit SATP mode Some RISC-V implementations may hang when attempting to write an unsupported SATP mode, even though the latest RISC-V specification states such writes should have no effect. To avoid this issue, the logic for selecting SATP mode has been refined: The kernel now determines the SATP mode limit by taking the minimum of the value specified by the kernel command line (noXlvl) and the "mmu-type" property in the device tree (FDT). If only one is specified, use that. - If the resulting limit is sv48 or higher, the kernel will probe SATP modes from this limit downward until a supported mode is found. - If the limit is sv39, the kernel will directly use sv39 without probing. This ensures SATP mode selection is safe and compatible with both hardware and user configuration, minimizing the risk of hangs. Signed-off-by: Junhui Liu Reviewed-by: Alexandre Ghiti Reviewed-by: Nutty Liu Link: https://lore.kernel.org/r/20250722-satp-from-fdt-v1-2-5ba22218fa5f@pigmoral.tech Signed-off-by: Paul Walmsley (cherry picked from commit 17e9521044c9b3ee839f861d1ac35c5b5c20d16b) Signed-off-by: Han Gao --- arch/riscv/kernel/pi/fdt_early.c | 40 ++++++++++++++++++++++++++++++++ arch/riscv/kernel/pi/pi.h | 1 + arch/riscv/mm/init.c | 11 ++++++--- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/pi/fdt_early.c b/arch/riscv/kernel/pi/fdt_early.c index 9bdee2fafe47e4..a12ff8090f1903 100644 --- a/arch/riscv/kernel/pi/fdt_early.c +++ b/arch/riscv/kernel/pi/fdt_early.c @@ -3,6 +3,7 @@ #include #include #include +#include #include "pi.h" @@ -183,3 +184,42 @@ bool fdt_early_match_extension_isa(const void *fdt, const char *ext_name) return ret; } + +/** + * set_satp_mode_from_fdt - determine SATP mode based on the MMU type in fdt + * + * @dtb_pa: physical address of the device tree blob + * + * Returns the SATP mode corresponding to the MMU type of the first enabled CPU, + * 0 otherwise + */ +u64 set_satp_mode_from_fdt(uintptr_t dtb_pa) +{ + const void *fdt = (const void *)dtb_pa; + const char *mmu_type; + int node, parent; + + parent = fdt_path_offset(fdt, "/cpus"); + if (parent < 0) + return 0; + + fdt_for_each_subnode(node, fdt, parent) { + if (!fdt_node_name_eq(fdt, node, "cpu")) + continue; + + if (!fdt_device_is_available(fdt, node)) + continue; + + mmu_type = fdt_getprop(fdt, node, "mmu-type", NULL); + if (!mmu_type) + break; + + if (!strcmp(mmu_type, "riscv,sv39")) + return SATP_MODE_39; + else if (!strcmp(mmu_type, "riscv,sv48")) + return SATP_MODE_48; + break; + } + + return 0; +} diff --git a/arch/riscv/kernel/pi/pi.h b/arch/riscv/kernel/pi/pi.h index 21141d84fea603..3fee2cfddf7cfb 100644 --- a/arch/riscv/kernel/pi/pi.h +++ b/arch/riscv/kernel/pi/pi.h @@ -14,6 +14,7 @@ u64 get_kaslr_seed(uintptr_t dtb_pa); u64 get_kaslr_seed_zkr(const uintptr_t dtb_pa); bool set_nokaslr_from_cmdline(uintptr_t dtb_pa); u64 set_satp_mode_from_cmdline(uintptr_t dtb_pa); +u64 set_satp_mode_from_fdt(uintptr_t dtb_pa); bool fdt_early_match_extension_isa(const void *fdt, const char *ext_name); diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 054265b3f26803..85cb70b10c0715 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -816,6 +816,7 @@ static __meminit pgprot_t pgprot_from_va(uintptr_t va) #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) u64 __pi_set_satp_mode_from_cmdline(uintptr_t dtb_pa); +u64 __pi_set_satp_mode_from_fdt(uintptr_t dtb_pa); static void __init disable_pgtable_l5(void) { @@ -855,18 +856,22 @@ static void __init set_mmap_rnd_bits_max(void) * underlying hardware: establish 1:1 mapping in 4-level page table mode * then read SATP to see if the configuration was taken into account * meaning sv48 is supported. + * The maximum SATP mode is limited by both the command line and the "mmu-type" + * property in the device tree, since some platforms may hang if an unsupported + * SATP mode is attempted. */ static __init void set_satp_mode(uintptr_t dtb_pa) { u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; - u64 satp_mode_cmdline = __pi_set_satp_mode_from_cmdline(dtb_pa); + u64 satp_mode_limit = min_not_zero(__pi_set_satp_mode_from_cmdline(dtb_pa), + __pi_set_satp_mode_from_fdt(dtb_pa)); kernel_map.page_offset = PAGE_OFFSET_L5; - if (satp_mode_cmdline == SATP_MODE_48) { + if (satp_mode_limit == SATP_MODE_48) { disable_pgtable_l5(); - } else if (satp_mode_cmdline == SATP_MODE_39) { + } else if (satp_mode_limit == SATP_MODE_39) { disable_pgtable_l5(); disable_pgtable_l4(); return; From 8e93611489e6524c7fdcdb9a614d0250ad7a98d1 Mon Sep 17 00:00:00 2001 From: "Guo Ren (Alibaba DAMO Academy)" Date: Sun, 13 Jul 2025 11:53:21 -0400 Subject: [PATCH 30/30] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup The early version of XuanTie C910 core has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren (Alibaba DAMO Academy) Link: https://lore.kernel.org/r/20250713155321.2064856-3-guoren@kernel.org Signed-off-by: Han Gao --- arch/riscv/Kconfig.errata | 17 ++++++++++ arch/riscv/errata/thead/errata.c | 20 ++++++++++++ arch/riscv/include/asm/errata_list_vendors.h | 3 +- arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ include/asm-generic/rwonce.h | 2 ++ 5 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/rwonce.h diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570de0..d2c982ba537304 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -130,4 +130,21 @@ config ERRATA_THEAD_GHOSTWRITE If you don't know what to do here, say "Y". +config ERRATA_THEAD_WRITE_ONCE + bool "Apply T-Head WRITE_ONCE errata" + depends on ERRATA_THEAD + default y + help + The early version of T-Head C9xx cores of sg2042 & th1520 have a store + merge buffer delay problem. The store merge buffer could improve the + store queue performance by merging multi-store requests, but when there + are no continued store requests, the prior single store request would be + waiting in the store queue for a long time. That would cause signifi- + cant problems for communication between multi-cores. Appending a + fence w.o could immediately flush the store merge buffer and let other + cores see the write result. + + This will apply the WRITE_ONCE errata to handle the non-standard beh- + avior via appending a fence w.o instruction for WRITE_ONCE(). + endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 0b942183f708fe..fbe46f2fa8fbbd 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, return true; } +static bool errata_probe_write_once(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) + return false; + + /* target-c9xx cores report arch_id and impid as 0 */ + if (arch_id != 0 || impid != 0) + return false; + + if (stage == RISCV_ALTERNATIVES_BOOT || + stage == RISCV_ALTERNATIVES_MODULE) + return true; + + return false; +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, errata_probe_ghostwrite(stage, archid, impid); + if (errata_probe_write_once(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); + return cpu_req_errata; } diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h index d448b9ce7c7c58..d29d33ce2197d8 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -18,7 +18,8 @@ #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_WRITE_ONCE 3 +#define ERRATA_THEAD_NUMBER 4 #endif #endif /* ASM_ERRATA_LIST_VENDORS_H */ diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h new file mode 100644 index 00000000000000..081793d4d772da --- /dev/null +++ b/arch/riscv/include/asm/rwonce.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_RWONCE_H +#define __ASM_RWONCE_H + +#include +#include +#include +#include + +#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) + +#define write_once_fence() \ +do { \ + asm volatile(ALTERNATIVE( \ + "nop", \ + "fence w, o", \ + THEAD_VENDOR_ID, \ + ERRATA_THEAD_WRITE_ONCE, \ + CONFIG_ERRATA_THEAD_WRITE_ONCE) \ + : : : "memory"); \ +} while (0) + +#define __WRITE_ONCE(x, val) \ +do { \ + *(volatile typeof(x) *)&(x) = (val); \ + write_once_fence(); \ +} while (0) + +#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ + +#include + +#endif /* __ASM_RWONCE_H */ diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 52b969c7cef935..4e2d941f15a11b 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -50,10 +50,12 @@ __READ_ONCE(x); \ }) +#ifndef __WRITE_ONCE #define __WRITE_ONCE(x, val) \ do { \ *(volatile typeof(x) *)&(x) = (val); \ } while (0) +#endif #define WRITE_ONCE(x, val) \ do { \