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- Add initial support for ARMv8A, ARMV7R and ARMV8R
- Added core_cxx.h files for ARMv8A, ARMV7R and ARMV8R based profiles - Moved gic peripheral to separate file - Moved __FPU_Enable function to the architecture specific file
1 parent 2f82b0d commit 00ed1eb

35 files changed

+3183
-1057
lines changed

CMSIS/Core/Include/core_ca.h renamed to CMSIS/Core/Include/a-profile/armv7a.h

Lines changed: 76 additions & 736 deletions
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CMSIS/Core/Include/a-profile/cmsis_cp15.h renamed to CMSIS/Core/Include/a-profile/armv7a_cp15.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
2+
* Copyright (c) 2009-2024 ARM Limited. All rights reserved.
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -362,10 +362,10 @@ __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
362362

363363
/******************************* VIRTUAL TIMER *******************************/
364364
/** see [ARM DDI 0406C.d] :
365-
. §B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register"
366-
. §B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register"
367-
. §B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register"
368-
. §B4.1.34 "CNTVCT, Counter-timer Virtual Count register"
365+
* B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register"
366+
* B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register"
367+
* B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register"
368+
* B4.1.34 "CNTVCT, Counter-timer Virtual Count register"
369369
**/
370370
/** \brief Set CNTV_TVAL
371371
This function assigns the given value to VL1 Virtual Timer Value Register (CNTV_TVAL).

‎CMSIS/Core/Include/a-profile/armv8a.h‎

Lines changed: 641 additions & 0 deletions
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‎CMSIS/Core/Include/a-profile/armv8a_cp15.h‎

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
/*
2+
* Copyright (c) 2009-2024 ARM Limited. All rights reserved.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the License); you may
7+
* not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
14+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
*/
18+
#include <stdint.h>
19+
20+
#if defined ( __ICCARM__ )
21+
#pragma system_include /* treat file as system include file for MISRA check */
22+
#elif defined (__clang__)
23+
#pragma clang system_header /* treat file as system include file */
24+
#endif
25+
26+
#ifndef __CMSIS_SYSTEM_CONTROL_H
27+
#define __CMSIS_SYSTEM_CONTROL_H
28+
29+
30+
/** \brief Get MPIDR EL1
31+
\return Multiprocessor Affinity Register value
32+
*/
33+
__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void)
34+
{
35+
uint64_t result;
36+
__ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory");
37+
return result;
38+
}
39+
40+
/** \brief Get MAIR EL3
41+
\return MAIR value
42+
*/
43+
__STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void)
44+
{
45+
uint64_t result;
46+
__ASM volatile("MRS %0, mair_el3" : "=r" (result) : : "memory");
47+
return result;
48+
}
49+
50+
/** \brief Set MAIR EL3
51+
\param [in] mair MAIR value to set
52+
*/
53+
__STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair)
54+
{
55+
__ASM volatile("MSR mair_el3, %0" : : "r" (mair) : "memory");
56+
}
57+
58+
/** \brief Get TCR EL3
59+
\return TCR value
60+
*/
61+
__STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void)
62+
{
63+
uint64_t result;
64+
__ASM volatile("MRS %0, tcr_el3" : "=r" (result) : : "memory");
65+
return result;
66+
}
67+
68+
/** \brief Set TCR EL3
69+
\param [in] tcr TCR value to set
70+
*/
71+
__STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr)
72+
{
73+
__ASM volatile("MSR tcr_el3, %0" : : "r" (tcr) : "memory");
74+
}
75+
76+
/** \brief Get TTBR0 EL3
77+
\return Translation Table Base Register 0 value
78+
*/
79+
__STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void)
80+
{
81+
uint64_t result;
82+
__ASM volatile("MRS %0, ttbr0_el3" : "=r" (result) : : "memory");
83+
return result;
84+
}
85+
86+
/** \brief Set TTBR0 EL3
87+
\param [in] ttbr0 Translation Table Base Register 0 value to set
88+
*/
89+
__STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0)
90+
{
91+
__ASM volatile("MSR ttbr0_el3, %0" : : "r" (ttbr0) : "memory");
92+
}
93+
94+
/** \brief Get SCTLR EL3
95+
\return STRLR EL3 value
96+
*/
97+
__STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void)
98+
{
99+
uint64_t result;
100+
__ASM volatile("MRS %0, sctlr_el3" : "=r" (result) : : "memory");
101+
return result;
102+
}
103+
104+
/** \brief Set SCTLR EL3
105+
\param [in] vbar SCTLR value to set
106+
*/
107+
__STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr)
108+
{
109+
__ASM volatile("MSR sctlr_el3, %0" : : "r" (sctlr) : "memory");
110+
}
111+
112+
/** \brief Set VBAR EL3
113+
\param [in] vbar VBAR value to set
114+
*/
115+
__STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar)
116+
{
117+
__ASM volatile("MSR vbar_el3, %0" : : "r" (vbar) : "memory");
118+
}
119+
120+
/** \brief Set VBAR EL2
121+
\param [in] vbar VBAR value to set
122+
*/
123+
__STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar)
124+
{
125+
__ASM volatile("MSR vbar_el2, %0" : : "r" (vbar) : "memory");
126+
}
127+
128+
/** \brief Set VBAR EL1
129+
\param [in] vbar VBAR value to set
130+
*/
131+
__STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar)
132+
{
133+
__ASM volatile("MSR vbar_el1, %0" : : "r" (vbar) : "memory");
134+
}
135+
136+
137+
#endif /* __CMSIS_SYSTEM_CONTROL_H */

‎CMSIS/Core/Include/a-profile/cmsis_armclang_a.h‎

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -317,76 +317,4 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
317317
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
318318
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
319319

320-
#include "cmsis_cp15.h"
321-
322-
/** \brief Enable Floating Point Unit
323-
324-
Critical section, called from undef handler, so systick is disabled
325-
*/
326-
__STATIC_INLINE void __FPU_Enable(void)
327-
{
328-
__ASM volatile(
329-
// Permit access to VFP/NEON, registers by modifying CPACR
330-
" MRC p15,0,R1,c1,c0,2 \n"
331-
" ORR R1,R1,#0x00F00000 \n"
332-
" MCR p15,0,R1,c1,c0,2 \n"
333-
334-
// Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
335-
" ISB \n"
336-
337-
// Enable VFP/NEON
338-
" VMRS R1,FPEXC \n"
339-
" ORR R1,R1,#0x40000000 \n"
340-
" VMSR FPEXC,R1 \n"
341-
342-
// Initialise VFP/NEON registers to 0
343-
" MOV R2,#0 \n"
344-
345-
// Initialise D16 registers to 0
346-
" VMOV D0, R2,R2 \n"
347-
" VMOV D1, R2,R2 \n"
348-
" VMOV D2, R2,R2 \n"
349-
" VMOV D3, R2,R2 \n"
350-
" VMOV D4, R2,R2 \n"
351-
" VMOV D5, R2,R2 \n"
352-
" VMOV D6, R2,R2 \n"
353-
" VMOV D7, R2,R2 \n"
354-
" VMOV D8, R2,R2 \n"
355-
" VMOV D9, R2,R2 \n"
356-
" VMOV D10,R2,R2 \n"
357-
" VMOV D11,R2,R2 \n"
358-
" VMOV D12,R2,R2 \n"
359-
" VMOV D13,R2,R2 \n"
360-
" VMOV D14,R2,R2 \n"
361-
" VMOV D15,R2,R2 \n"
362-
363-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
364-
// Initialise D32 registers to 0
365-
" VMOV D16,R2,R2 \n"
366-
" VMOV D17,R2,R2 \n"
367-
" VMOV D18,R2,R2 \n"
368-
" VMOV D19,R2,R2 \n"
369-
" VMOV D20,R2,R2 \n"
370-
" VMOV D21,R2,R2 \n"
371-
" VMOV D22,R2,R2 \n"
372-
" VMOV D23,R2,R2 \n"
373-
" VMOV D24,R2,R2 \n"
374-
" VMOV D25,R2,R2 \n"
375-
" VMOV D26,R2,R2 \n"
376-
" VMOV D27,R2,R2 \n"
377-
" VMOV D28,R2,R2 \n"
378-
" VMOV D29,R2,R2 \n"
379-
" VMOV D30,R2,R2 \n"
380-
" VMOV D31,R2,R2 \n"
381-
#endif
382-
383-
// Initialise FPSCR to a known state
384-
" VMRS R1,FPSCR \n"
385-
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
386-
" AND R1,R1,R2 \n"
387-
" VMSR FPSCR,R1 "
388-
: : : "cc", "r1", "r2"
389-
);
390-
}
391-
392320
#endif /* __CMSIS_ARMCLANG_A_H */

‎CMSIS/Core/Include/a-profile/cmsis_clang_a.h‎

Lines changed: 1 addition & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#ifndef __CMSIS_CLANG_H
2929
#error "This file must not be included directly"
3030
#endif
31+
3132
/**
3233
\brief STRT Unprivileged (8 bit)
3334
\details Executes a Unprivileged STRT instruction for 8 bit values.
@@ -313,72 +314,6 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
313314
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
314315
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
315316

316-
#include "cmsis_cp15.h"
317-
318-
/** \brief Enable Floating Point Unit
319-
320-
Critical section, called from undef handler, so systick is disabled
321-
*/
322-
__STATIC_INLINE void __FPU_Enable(void)
323-
{
324-
// Permit access to VFP/NEON, registers by modifying CPACR
325-
const uint32_t cpacr = __get_CPACR();
326-
__set_CPACR(cpacr | 0x00F00000ul);
327-
__ISB();
328-
329-
// Enable VFP/NEON
330-
const uint32_t fpexc = __get_FPEXC();
331-
__set_FPEXC(fpexc | 0x40000000ul);
332-
333-
__ASM volatile(
334-
// Initialise VFP/NEON registers to 0
335-
" MOV R2,#0 \n"
336-
337-
// Initialise D16 registers to 0
338-
" VMOV D0, R2,R2 \n"
339-
" VMOV D1, R2,R2 \n"
340-
" VMOV D2, R2,R2 \n"
341-
" VMOV D3, R2,R2 \n"
342-
" VMOV D4, R2,R2 \n"
343-
" VMOV D5, R2,R2 \n"
344-
" VMOV D6, R2,R2 \n"
345-
" VMOV D7, R2,R2 \n"
346-
" VMOV D8, R2,R2 \n"
347-
" VMOV D9, R2,R2 \n"
348-
" VMOV D10,R2,R2 \n"
349-
" VMOV D11,R2,R2 \n"
350-
" VMOV D12,R2,R2 \n"
351-
" VMOV D13,R2,R2 \n"
352-
" VMOV D14,R2,R2 \n"
353-
" VMOV D15,R2,R2 \n"
354-
355-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
356-
// Initialise D32 registers to 0
357-
" VMOV D16,R2,R2 \n"
358-
" VMOV D17,R2,R2 \n"
359-
" VMOV D18,R2,R2 \n"
360-
" VMOV D19,R2,R2 \n"
361-
" VMOV D20,R2,R2 \n"
362-
" VMOV D21,R2,R2 \n"
363-
" VMOV D22,R2,R2 \n"
364-
" VMOV D23,R2,R2 \n"
365-
" VMOV D24,R2,R2 \n"
366-
" VMOV D25,R2,R2 \n"
367-
" VMOV D26,R2,R2 \n"
368-
" VMOV D27,R2,R2 \n"
369-
" VMOV D28,R2,R2 \n"
370-
" VMOV D29,R2,R2 \n"
371-
" VMOV D30,R2,R2 \n"
372-
" VMOV D31,R2,R2 \n"
373-
#endif
374-
: : : "cc", "r2"
375-
);
376-
377-
// Initialise FPSCR to a known state
378-
const uint32_t fpscr = __get_FPSCR();
379-
__set_FPSCR(fpscr & 0x00086060ul);
380-
}
381-
382317
/*@} end of group CMSIS_Core_intrinsics */
383318

384319
#pragma clang diagnostic pop

‎CMSIS/Core/Include/a-profile/cmsis_gcc_a.h‎

Lines changed: 0 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -150,72 +150,6 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
150150
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
151151
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
152152

153-
#include "cmsis_cp15.h"
154-
155-
/** \brief Enable Floating Point Unit
156-
157-
Critical section, called from undef handler, so systick is disabled
158-
*/
159-
__STATIC_INLINE void __FPU_Enable(void)
160-
{
161-
// Permit access to VFP/NEON, registers by modifying CPACR
162-
const uint32_t cpacr = __get_CPACR();
163-
__set_CPACR(cpacr | 0x00F00000ul);
164-
__ISB();
165-
166-
// Enable VFP/NEON
167-
const uint32_t fpexc = __get_FPEXC();
168-
__set_FPEXC(fpexc | 0x40000000ul);
169-
170-
__ASM volatile(
171-
// Initialise VFP/NEON registers to 0
172-
" MOV R2,#0 \n"
173-
174-
// Initialise D16 registers to 0
175-
" VMOV D0, R2,R2 \n"
176-
" VMOV D1, R2,R2 \n"
177-
" VMOV D2, R2,R2 \n"
178-
" VMOV D3, R2,R2 \n"
179-
" VMOV D4, R2,R2 \n"
180-
" VMOV D5, R2,R2 \n"
181-
" VMOV D6, R2,R2 \n"
182-
" VMOV D7, R2,R2 \n"
183-
" VMOV D8, R2,R2 \n"
184-
" VMOV D9, R2,R2 \n"
185-
" VMOV D10,R2,R2 \n"
186-
" VMOV D11,R2,R2 \n"
187-
" VMOV D12,R2,R2 \n"
188-
" VMOV D13,R2,R2 \n"
189-
" VMOV D14,R2,R2 \n"
190-
" VMOV D15,R2,R2 \n"
191-
192-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
193-
// Initialise D32 registers to 0
194-
" VMOV D16,R2,R2 \n"
195-
" VMOV D17,R2,R2 \n"
196-
" VMOV D18,R2,R2 \n"
197-
" VMOV D19,R2,R2 \n"
198-
" VMOV D20,R2,R2 \n"
199-
" VMOV D21,R2,R2 \n"
200-
" VMOV D22,R2,R2 \n"
201-
" VMOV D23,R2,R2 \n"
202-
" VMOV D24,R2,R2 \n"
203-
" VMOV D25,R2,R2 \n"
204-
" VMOV D26,R2,R2 \n"
205-
" VMOV D27,R2,R2 \n"
206-
" VMOV D28,R2,R2 \n"
207-
" VMOV D29,R2,R2 \n"
208-
" VMOV D30,R2,R2 \n"
209-
" VMOV D31,R2,R2 \n"
210-
#endif
211-
: : : "cc", "r2"
212-
);
213-
214-
// Initialise FPSCR to a known state
215-
const uint32_t fpscr = __get_FPSCR();
216-
__set_FPSCR(fpscr & 0x00086060ul);
217-
}
218-
219153
/*@} end of group CMSIS_Core_intrinsics */
220154

221155
#pragma GCC diagnostic pop

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