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Masmiseim36JonatanAntoni
Masmiseim36
authored and
JonatanAntoni
committed
- Add initial support for ARMv8A, ARMV7R and ARMV8R
- Added core_cxx.h files for ARMv8A, ARMV7R and ARMV8R based profiles - Moved gic peripheral to separate file - Moved __FPU_Enable function to the architecture specific file
1 parent 5d06d1d commit bc0287b

27 files changed

+3065
-965
lines changed

CMSIS/Core/Include/core_ca.h renamed to CMSIS/Core/Include/a-profile/armv7a.h

Lines changed: 88 additions & 744 deletions
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CMSIS/Core/Include/a-profile/cmsis_cp15.h renamed to CMSIS/Core/Include/a-profile/armv7a_cp15.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
2-
* @file cmsis_cp15.h
2+
* @file armv7a_cp15.h
33
* @brief CMSIS compiler specific macros, functions, instructions
44
* @version V1.0.2
55
* @date 19. December 2022
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
8+
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*

‎CMSIS/Core/Include/a-profile/armv8a.h‎

Lines changed: 647 additions & 0 deletions
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‎CMSIS/Core/Include/a-profile/armv8a_cp15.h‎

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,143 @@
1+
/**************************************************************************//**
2+
* @file armv8a_cp15.h
3+
* @brief CMSIS compiler specific macros, functions, instructions
4+
* @version V6.0.0
5+
* @date 4. August 2023
6+
******************************************************************************/
7+
/*
8+
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
9+
*
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the License); you may
13+
* not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
20+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
*/
24+
#include <stdint.h>
25+
26+
#if defined ( __ICCARM__ )
27+
#pragma system_include /* treat file as system include file for MISRA check */
28+
#elif defined (__clang__)
29+
#pragma clang system_header /* treat file as system include file */
30+
#endif
31+
32+
#ifndef __CMSIS_SYSTEM_CONTROL_H
33+
#define __CMSIS_SYSTEM_CONTROL_H
34+
35+
36+
/** \brief Get MPIDR EL1
37+
\return Multiprocessor Affinity Register value
38+
*/
39+
__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void)
40+
{
41+
uint64_t result;
42+
__ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory");
43+
return result;
44+
}
45+
46+
/** \brief Get MAIR EL3
47+
\return MAIR value
48+
*/
49+
__STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void)
50+
{
51+
uint64_t result;
52+
__ASM volatile("MRS %0, mair_el3" : "=r" (result) : : "memory");
53+
return result;
54+
}
55+
56+
/** \brief Set MAIR EL3
57+
\param [in] mair MAIR value to set
58+
*/
59+
__STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair)
60+
{
61+
__ASM volatile("MSR mair_el3, %0" : : "r" (mair) : "memory");
62+
}
63+
64+
/** \brief Get TCR EL3
65+
\return TCR value
66+
*/
67+
__STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void)
68+
{
69+
uint64_t result;
70+
__ASM volatile("MRS %0, tcr_el3" : "=r" (result) : : "memory");
71+
return result;
72+
}
73+
74+
/** \brief Set TCR EL3
75+
\param [in] tcr TCR value to set
76+
*/
77+
__STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr)
78+
{
79+
__ASM volatile("MSR tcr_el3, %0" : : "r" (tcr) : "memory");
80+
}
81+
82+
/** \brief Get TTBR0 EL3
83+
\return Translation Table Base Register 0 value
84+
*/
85+
__STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void)
86+
{
87+
uint64_t result;
88+
__ASM volatile("MRS %0, ttbr0_el3" : "=r" (result) : : "memory");
89+
return result;
90+
}
91+
92+
/** \brief Set TTBR0 EL3
93+
\param [in] ttbr0 Translation Table Base Register 0 value to set
94+
*/
95+
__STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0)
96+
{
97+
__ASM volatile("MSR ttbr0_el3, %0" : : "r" (ttbr0) : "memory");
98+
}
99+
100+
/** \brief Get SCTLR EL3
101+
\return STRLR EL3 value
102+
*/
103+
__STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void)
104+
{
105+
uint64_t result;
106+
__ASM volatile("MRS %0, sctlr_el3" : "=r" (result) : : "memory");
107+
return result;
108+
}
109+
110+
/** \brief Set SCTLR EL3
111+
\param [in] vbar SCTLR value to set
112+
*/
113+
__STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr)
114+
{
115+
__ASM volatile("MSR sctlr_el3, %0" : : "r" (sctlr) : "memory");
116+
}
117+
118+
/** \brief Set VBAR EL3
119+
\param [in] vbar VBAR value to set
120+
*/
121+
__STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar)
122+
{
123+
__ASM volatile("MSR vbar_el3, %0" : : "r" (vbar) : "memory");
124+
}
125+
126+
/** \brief Set VBAR EL2
127+
\param [in] vbar VBAR value to set
128+
*/
129+
__STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar)
130+
{
131+
__ASM volatile("MSR vbar_el2, %0" : : "r" (vbar) : "memory");
132+
}
133+
134+
/** \brief Set VBAR EL1
135+
\param [in] vbar VBAR value to set
136+
*/
137+
__STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar)
138+
{
139+
__ASM volatile("MSR vbar_el1, %0" : : "r" (vbar) : "memory");
140+
}
141+
142+
143+
#endif /* __CMSIS_SYSTEM_CONTROL_H */

‎CMSIS/Core/Include/a-profile/cmsis_armclang_a.h‎

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -698,76 +698,4 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
698698
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
699699
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
700700

701-
#include "cmsis_cp15.h"
702-
703-
/** \brief Enable Floating Point Unit
704-
705-
Critical section, called from undef handler, so systick is disabled
706-
*/
707-
__STATIC_INLINE void __FPU_Enable(void)
708-
{
709-
__ASM volatile(
710-
//Permit access to VFP/NEON, registers by modifying CPACR
711-
" MRC p15,0,R1,c1,c0,2 \n"
712-
" ORR R1,R1,#0x00F00000 \n"
713-
" MCR p15,0,R1,c1,c0,2 \n"
714-
715-
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
716-
" ISB \n"
717-
718-
//Enable VFP/NEON
719-
" VMRS R1,FPEXC \n"
720-
" ORR R1,R1,#0x40000000 \n"
721-
" VMSR FPEXC,R1 \n"
722-
723-
//Initialise VFP/NEON registers to 0
724-
" MOV R2,#0 \n"
725-
726-
//Initialise D16 registers to 0
727-
" VMOV D0, R2,R2 \n"
728-
" VMOV D1, R2,R2 \n"
729-
" VMOV D2, R2,R2 \n"
730-
" VMOV D3, R2,R2 \n"
731-
" VMOV D4, R2,R2 \n"
732-
" VMOV D5, R2,R2 \n"
733-
" VMOV D6, R2,R2 \n"
734-
" VMOV D7, R2,R2 \n"
735-
" VMOV D8, R2,R2 \n"
736-
" VMOV D9, R2,R2 \n"
737-
" VMOV D10,R2,R2 \n"
738-
" VMOV D11,R2,R2 \n"
739-
" VMOV D12,R2,R2 \n"
740-
" VMOV D13,R2,R2 \n"
741-
" VMOV D14,R2,R2 \n"
742-
" VMOV D15,R2,R2 \n"
743-
744-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
745-
//Initialise D32 registers to 0
746-
" VMOV D16,R2,R2 \n"
747-
" VMOV D17,R2,R2 \n"
748-
" VMOV D18,R2,R2 \n"
749-
" VMOV D19,R2,R2 \n"
750-
" VMOV D20,R2,R2 \n"
751-
" VMOV D21,R2,R2 \n"
752-
" VMOV D22,R2,R2 \n"
753-
" VMOV D23,R2,R2 \n"
754-
" VMOV D24,R2,R2 \n"
755-
" VMOV D25,R2,R2 \n"
756-
" VMOV D26,R2,R2 \n"
757-
" VMOV D27,R2,R2 \n"
758-
" VMOV D28,R2,R2 \n"
759-
" VMOV D29,R2,R2 \n"
760-
" VMOV D30,R2,R2 \n"
761-
" VMOV D31,R2,R2 \n"
762-
#endif
763-
764-
//Initialise FPSCR to a known state
765-
" VMRS R1,FPSCR \n"
766-
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
767-
" AND R1,R1,R2 \n"
768-
" VMSR FPSCR,R1 "
769-
: : : "cc", "r1", "r2"
770-
);
771-
}
772-
773701
#endif /* __CMSIS_ARMCLANG_A_H */

‎CMSIS/Core/Include/a-profile/cmsis_gcc_a.h‎

Lines changed: 0 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -862,72 +862,6 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
862862
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
863863
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
864864

865-
#include "cmsis_cp15.h"
866-
867-
/** \brief Enable Floating Point Unit
868-
869-
Critical section, called from undef handler, so systick is disabled
870-
*/
871-
__STATIC_INLINE void __FPU_Enable(void)
872-
{
873-
// Permit access to VFP/NEON, registers by modifying CPACR
874-
const uint32_t cpacr = __get_CPACR();
875-
__set_CPACR(cpacr | 0x00F00000ul);
876-
__ISB();
877-
878-
// Enable VFP/NEON
879-
const uint32_t fpexc = __get_FPEXC();
880-
__set_FPEXC(fpexc | 0x40000000ul);
881-
882-
__ASM volatile(
883-
// Initialise VFP/NEON registers to 0
884-
" MOV R2,#0 \n"
885-
886-
// Initialise D16 registers to 0
887-
" VMOV D0, R2,R2 \n"
888-
" VMOV D1, R2,R2 \n"
889-
" VMOV D2, R2,R2 \n"
890-
" VMOV D3, R2,R2 \n"
891-
" VMOV D4, R2,R2 \n"
892-
" VMOV D5, R2,R2 \n"
893-
" VMOV D6, R2,R2 \n"
894-
" VMOV D7, R2,R2 \n"
895-
" VMOV D8, R2,R2 \n"
896-
" VMOV D9, R2,R2 \n"
897-
" VMOV D10,R2,R2 \n"
898-
" VMOV D11,R2,R2 \n"
899-
" VMOV D12,R2,R2 \n"
900-
" VMOV D13,R2,R2 \n"
901-
" VMOV D14,R2,R2 \n"
902-
" VMOV D15,R2,R2 \n"
903-
904-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
905-
// Initialise D32 registers to 0
906-
" VMOV D16,R2,R2 \n"
907-
" VMOV D17,R2,R2 \n"
908-
" VMOV D18,R2,R2 \n"
909-
" VMOV D19,R2,R2 \n"
910-
" VMOV D20,R2,R2 \n"
911-
" VMOV D21,R2,R2 \n"
912-
" VMOV D22,R2,R2 \n"
913-
" VMOV D23,R2,R2 \n"
914-
" VMOV D24,R2,R2 \n"
915-
" VMOV D25,R2,R2 \n"
916-
" VMOV D26,R2,R2 \n"
917-
" VMOV D27,R2,R2 \n"
918-
" VMOV D28,R2,R2 \n"
919-
" VMOV D29,R2,R2 \n"
920-
" VMOV D30,R2,R2 \n"
921-
" VMOV D31,R2,R2 \n"
922-
#endif
923-
: : : "cc", "r2"
924-
);
925-
926-
// Initialise FPSCR to a known state
927-
const uint32_t fpscr = __get_FPSCR();
928-
__set_FPSCR(fpscr & 0x00086060ul);
929-
}
930-
931865
/*@} end of group CMSIS_Core_intrinsics */
932866

933867
#pragma GCC diagnostic pop

‎CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h‎

Lines changed: 0 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -273,8 +273,6 @@
273273
#define __set_CP64(cp, op1, Rt, CRm) \
274274
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
275275

276-
#include "cmsis_cp15.h"
277-
278276
#define __NOP __iar_builtin_no_operation
279277

280278
#define __CLZ __iar_builtin_CLZ
@@ -495,75 +493,6 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
495493

496494
#define __get_mode() (__get_CPSR() & 0x1FU)
497495

498-
__STATIC_INLINE
499-
void __FPU_Enable(void)
500-
{
501-
__ASM volatile(
502-
//Permit access to VFP/NEON, registers by modifying CPACR
503-
" MRC p15,0,R1,c1,c0,2 \n"
504-
" ORR R1,R1,#0x00F00000 \n"
505-
" MCR p15,0,R1,c1,c0,2 \n"
506-
507-
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
508-
" ISB \n"
509-
510-
//Enable VFP/NEON
511-
" VMRS R1,FPEXC \n"
512-
" ORR R1,R1,#0x40000000 \n"
513-
" VMSR FPEXC,R1 \n"
514-
515-
//Initialise VFP/NEON registers to 0
516-
" MOV R2,#0 \n"
517-
518-
//Initialise D16 registers to 0
519-
" VMOV D0, R2,R2 \n"
520-
" VMOV D1, R2,R2 \n"
521-
" VMOV D2, R2,R2 \n"
522-
" VMOV D3, R2,R2 \n"
523-
" VMOV D4, R2,R2 \n"
524-
" VMOV D5, R2,R2 \n"
525-
" VMOV D6, R2,R2 \n"
526-
" VMOV D7, R2,R2 \n"
527-
" VMOV D8, R2,R2 \n"
528-
" VMOV D9, R2,R2 \n"
529-
" VMOV D10,R2,R2 \n"
530-
" VMOV D11,R2,R2 \n"
531-
" VMOV D12,R2,R2 \n"
532-
" VMOV D13,R2,R2 \n"
533-
" VMOV D14,R2,R2 \n"
534-
" VMOV D15,R2,R2 \n"
535-
536-
#ifdef __ARM_ADVANCED_SIMD__
537-
//Initialise D32 registers to 0
538-
" VMOV D16,R2,R2 \n"
539-
" VMOV D17,R2,R2 \n"
540-
" VMOV D18,R2,R2 \n"
541-
" VMOV D19,R2,R2 \n"
542-
" VMOV D20,R2,R2 \n"
543-
" VMOV D21,R2,R2 \n"
544-
" VMOV D22,R2,R2 \n"
545-
" VMOV D23,R2,R2 \n"
546-
" VMOV D24,R2,R2 \n"
547-
" VMOV D25,R2,R2 \n"
548-
" VMOV D26,R2,R2 \n"
549-
" VMOV D27,R2,R2 \n"
550-
" VMOV D28,R2,R2 \n"
551-
" VMOV D29,R2,R2 \n"
552-
" VMOV D30,R2,R2 \n"
553-
" VMOV D31,R2,R2 \n"
554-
#endif
555-
556-
//Initialise FPSCR to a known state
557-
" VMRS R1,FPSCR \n"
558-
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
559-
" AND R1,R1,R2 \n"
560-
" VMSR FPSCR,R1 \n"
561-
: : : "cc", "r1", "r2"
562-
);
563-
}
564-
565-
566-
567496
#undef __IAR_FT
568497
#undef __ICCARM_V8
569498

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