diff --git a/.github/workflows/core.yml b/.github/workflows/core.yml
index 797a7785d..2c6fb80d6 100644
--- a/.github/workflows/core.yml
+++ b/.github/workflows/core.yml
@@ -20,6 +20,7 @@ jobs:
 
     env:
       ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}
+      IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
 
     steps:
       - uses: actions/checkout@v5
@@ -39,12 +40,12 @@ jobs:
           sudo apt-get update
           sudo apt-get install libtinfo5 llvm-15-tools
           sudo ln -s /usr/bin/FileCheck-15 /usr/bin/FileCheck
-    
+     
       - name: Activate vcpkg environment
         uses: ARM-software/cmsis-actions/vcpkg@v1
         with:
           config: ./CMSIS/Core/Test/vcpkg-configuration.json
-          
+
       - name: Activate Arm tool license
         uses: ARM-software/cmsis-actions/armlm@v1
         with:
@@ -57,6 +58,13 @@ jobs:
         run: |
           ./build.py lit
 
+      - name: Archive Test Results
+        if: ${{ !cancelled() }}
+        uses: actions/upload-artifact@v4
+        with:
+          name: lit-test-results
+          path: ./CMSIS/Core/Test/*.xunit
+
       - name: Publish Test Results
         if: ${{ !cancelled() }}
         uses: EnricoMi/publish-unit-test-result-action@v2
diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml
index bc589cd58..4d245dfa0 100644
--- a/.github/workflows/corevalidation.yml
+++ b/.github/workflows/corevalidation.yml
@@ -10,23 +10,24 @@ on:
       - CMSIS/CoreValidation/**/*
   push:
     branches: [main]
-  
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.ref }}
   cancel-in-progress: true
 
 jobs:
   build-and-run:
-    
+
     strategy:
       fail-fast: true
       matrix:
-        compiler: [AC6, GCC, Clang]
-    
+        compiler: [AC6, GCC, Clang, IAR]
+
     runs-on: ubuntu-22.04
 
     env:
       ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}
+      IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
 
     steps:
       - run: |
@@ -49,7 +50,7 @@ jobs:
 
       - uses: actions/setup-python@v5
         with:
-          python-version: '3.10'    
+          python-version: '3.10'
           cache: 'pip'
 
       - name: Python requirements
@@ -62,17 +63,17 @@ jobs:
         run: |
           sudo apt-get update
           sudo apt-get install libtinfo5
-    
+
       - name: Activate vcpkg environment
         uses: ARM-software/cmsis-actions/vcpkg@v1
         with:
           config: ./CMSIS/CoreValidation/Project/vcpkg-configuration.json
-          
+
       - name: Activate Arm tool license
         uses: ARM-software/cmsis-actions/armlm@v1
         with:
           code: "${{ env.ARM_UBL_ACTIVATION_CODE }}"
-      
+
       - name: Initialize CodeQL
         if: matrix.compiler == 'GCC'
         uses: github/codeql-action/init@v3
@@ -85,6 +86,7 @@ jobs:
 
       - name: Build
         working-directory: ./CMSIS/CoreValidation/Project
+        shell: bash
         run: |
           echo "Register local Cortex_DFP pack"
           cpackget add /home/runner/Cortex_DFP/ARM.Cortex_DFP.pdsc
@@ -98,7 +100,7 @@ jobs:
 
       - name: Execute
         working-directory: ./CMSIS/CoreValidation/Project
-        run: |     
+        run: |
           echo "Run test projects ..."
           ./build.py --verbose -c ${{ matrix.compiler }} -d "CM*" run || echo "::warning::==== Some configurations failed to run! ==="
 
diff --git a/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h
index 381935fc5..80a886342 100644
--- a/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h
+++ b/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h
@@ -206,8 +206,7 @@ __iar_builtin_ISB();
 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
 
 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
-     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
   // without main extensions, the non-secure PSPLIM is RAZ/WI
   #define __TZ_get_PSPLIM_NS()      (0U)
   #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
diff --git a/CMSIS/Core/Test/README.md b/CMSIS/Core/Test/README.md
index fc6d974dc..a89dc79d5 100644
--- a/CMSIS/Core/Test/README.md
+++ b/CMSIS/Core/Test/README.md
@@ -25,6 +25,7 @@ Currently, the following build configurations are provided:
    - Arm Compiler 6 (AC6)
    - GNU Compiler (GCC)
    - LLVM/Clang (Clang)
+   - IAR Toolchain (IAR)
 2. Devices
    - Cortex-M0
    - Cortex-M0+
@@ -76,6 +77,7 @@ The following tools are required to build and run the Core tests:
 - [Arm Compiler 6.23](https://artifacts.tools.arm.com/arm-compiler/6.23/32/)*
 - [GCC Compiler 14.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/14.2.1/)*
 - [Clang Compiler 20.1.0](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-20.1.0)*
+- [IAR Toolchain 9.70.1](https://github.com/iarsystems/arm/releases/tag/9.70.1)*
 - [Python 3.9](https://www.python.org/downloads/)
 - [LLVM FileCheck](https://github.com/llvm/llvm-project/releases/)
   - Ubuntu package `llvm-<version>-tools`
diff --git a/CMSIS/Core/Test/build.py b/CMSIS/Core/Test/build.py
index 8f62ccca4..1a5c25319 100755
--- a/CMSIS/Core/Test/build.py
+++ b/CMSIS/Core/Test/build.py
@@ -82,11 +82,6 @@ def run_lit(toolchain, device, optimize):
     return ["lit", "--xunit-xml-output", f"lit.xml", "-D", f"toolchain={toolchain}", "-D", f"device={device}", "-D", f"optimize={optimize}", "src" ]
 
 
-@matrix_filter
-def filter_iar(config):
-    return config.compiler == CompilerAxis.IAR
-
-
 @matrix_filter
 def filter_gcc_cm52(config):
     device = config.device.match('CM52*')
diff --git a/CMSIS/Core/Test/lit.cfg.py b/CMSIS/Core/Test/lit.cfg.py
index d79d21ab3..1b8f9acb1 100644
--- a/CMSIS/Core/Test/lit.cfg.py
+++ b/CMSIS/Core/Test/lit.cfg.py
@@ -117,7 +117,7 @@
         'triple': 'thumbv7-em',
         'abi': 'eabi',
         'mcpu': 'cortex-m7',
-        'mfpu': 'fpv4-sp-d16',
+        'mfpu': 'fpv5-sp-d16',
         'mpu': True,
         'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm7.h',
@@ -847,6 +847,54 @@ def get_ccflags(self):
 
         return ccflags
     
+class Toolchain_IAR(Toolchain):
+    OPTIMIZE = {
+        'none': '-On',
+        'balanced': '-Oh',
+        'speed': '-Ohs',
+        'size': '-Ohz'
+    }
+    FPU = {
+        'none': 'none',
+        'fpv4-sp-d16': 'VFPv4-SP',
+        'fpv5-sp-d16': 'VFPv5-SP',
+        'fpv5-d16': 'VFPv5_D16',
+        'neon-vfpv3': 'VFPv3',
+        'neon-vfpv4': 'VFPv4',
+    }
+    CPU = {
+        'CA5': 'Cortex-A5',
+        'CA5neon': 'Cortex-A5.neon',
+        'CA7': 'Cortex-A7.no_neon',
+        'CA7neon': 'Cortex-A7',
+        'CA9': 'Cortex-A9.no_neon',
+        'CA9neon': 'Cortex-A9',
+    }
+    def __init__(self, **args):
+        super().__init__('IAR', **args)
+
+    def get_cc(self):
+        return os.path.join(self.get_root(), 'iccarm')
+    
+    def cpu(self):
+        if self.device in self.CPU:
+            return self.CPU[self.device]
+        return DEVICES[self.device]["mcpu"]
+
+    def fpu(self):
+        return self.FPU[DEVICES[self.device]["mfpu"]]
+
+    def get_ccflags(self):
+        ccflags = [
+            self.OPTIMIZE[self.optimize], 
+            f'--cpu={self.cpu()}', f'--fpu={self.fpu()}', 
+            '-I', os.path.abspath('../Include'), '-c', '-D', f'CORE_HEADER="{DEVICES[device]["header"]}"']
+        if device.endswith('S') and not device.endswith('NS'):
+            ccflags += ["--cmse"]
+        ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ()))
+
+        return ccflags
+    
 tc = None
 if toolchain == 'AC6':
     tc = Toolchain_AC6(device=device, optimize=optimize)
@@ -854,6 +902,9 @@ def get_ccflags(self):
     tc = Toolchain_GCC(device=device, optimize=optimize)
 elif toolchain == 'Clang':
     tc = Toolchain_Clang(device=device, optimize=optimize)
+elif toolchain == 'IAR':
+    tc = Toolchain_IAR(device=device, optimize=optimize)
+    config.environment['IAR_LMS_BEARER_TOKEN'] = os.environ.get('IAR_LMS_BEARER_TOKEN')
 
 prefixes = ['CHECK']
 if device.endswith('NS'):
@@ -864,6 +915,10 @@ def get_ccflags(self):
     prefixes += ['CHECK-THUMB']       
 elif DEVICES[device]['arch'].startswith('arm'):
     prefixes += ['CHECK-ARM']
+if toolchain == 'IAR':
+    prefixes += ['CHECK-IAR']
+else:
+    prefixes += ['CHECK-NON-IAR']
 
 if DEVICES[device]["mfpu"] != 'none':
     config.available_features.add('fpu')
diff --git a/CMSIS/Core/Test/src/cpsr.c b/CMSIS/Core/Test/src/cpsr.c
index 931c36683..35c47ec1c 100644
--- a/CMSIS/Core/Test/src/cpsr.c
+++ b/CMSIS/Core/Test/src/cpsr.c
@@ -22,7 +22,7 @@ void set_cpsr() {
 void get_mode() {
     // CHECK-LABEL: <get_mode>:
     // CHECK: mrs [[REG:r[0-9]+]], apsr
-    // CHECK: and [[REG]], [[REG]], #{{31|0x1f}}
+    // CHECK: and{{s?}} [[REG]], [[REG]], #{{31|0x1f}}
     volatile uint32_t result = __get_mode();
     // CHECK: {{(bx lr)|(pop {.*pc})}}
 }
diff --git a/CMSIS/Core/Test/src/noreturn.c b/CMSIS/Core/Test/src/noreturn.c
index 024d25786..f234e3544 100644
--- a/CMSIS/Core/Test/src/noreturn.c
+++ b/CMSIS/Core/Test/src/noreturn.c
@@ -9,7 +9,7 @@ static void func() {
 
 void noreturn() {
     // CHECK-LABEL: <noreturn>:
-    // CHECK: b 0x0 <noreturn>
+    // CHECK: {{b|bl}} {{0x[0-9a-fA-F]+}} <noreturn{{.*}}>
     func();
     // CHECK-NOT: bx lr
 }
diff --git a/CMSIS/Core/Test/src/ror.c b/CMSIS/Core/Test/src/ror.c
index 479760bb7..b7dec2b31 100644
--- a/CMSIS/Core/Test/src/ror.c
+++ b/CMSIS/Core/Test/src/ror.c
@@ -7,8 +7,8 @@ static volatile uint32_t b = 2u;
 
 void ror() {
     // CHECK-LABEL: <ror>:
-    // CHECK-THUMB: ror{{ne|s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
-    // CHECK-ARM: {{ror|rorne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-THUMB: ror{{ne|s|.w|s.w}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t c = __ROR(a, b);
     // CHECK: {{(bx lr)|(pop {.*pc})}}
 }
diff --git a/CMSIS/Core/Test/src/rrx.c b/CMSIS/Core/Test/src/rrx.c
index 76efca274..a7b0dfe7c 100644
--- a/CMSIS/Core/Test/src/rrx.c
+++ b/CMSIS/Core/Test/src/rrx.c
@@ -7,7 +7,7 @@ static volatile uint32_t a = 10u;
 
 void rrx() {
     // CHECK-LABEL: <rrx>:
-    // CHECK: rrx {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK: {{rrx|rrxs}} {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t c = __RRX(a);
     // CHECK: {{(bx lr)|(pop {.*pc})}}
 }
diff --git a/CMSIS/Core/Test/src/simd.c b/CMSIS/Core/Test/src/simd.c
index 4d6b3a4a2..931f10853 100644
--- a/CMSIS/Core/Test/src/simd.c
+++ b/CMSIS/Core/Test/src/simd.c
@@ -471,23 +471,29 @@ void pkhtb() {
 
 void sxtb16_ror() {    
     // CHECK-LABEL: <sxtb16_ror>:
-    // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #8
+    // CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #8
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#8|#0x8}}
+    // CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t result = __SXTB16_RORn(s32_1, 8);
 
-    // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #16
+    // CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #16
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#16|#0x10}}
+    // CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
     result = __SXTB16_RORn(s32_1, 16);
 
-    // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24
+    // CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#24|#0x18}}
+    // CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
     result = __SXTB16_RORn(s32_1, 24);
 
-    // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
-    // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-THUMB: ror{{s?}}.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-ARM: ror{{s?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
     // CHECK: sxtb16 {{r[0-9]+}}, [[REG]]
     // CHECK-NOT: , ror
     result = __SXTB16_RORn(s32_1, 5);
 
     // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
-    // CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK-NOT: , ror
     result = __SXTB16_RORn(s32_1, u8);
@@ -498,23 +504,29 @@ void sxtb16_ror() {
 void sxtab16_ror() {
     // CHECK-LABEL: <sxtab16_ror>:
 
-    // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #8
+    // CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #8
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#8|#0x8}}
+    // CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t result = __SXTAB16_RORn(s32_1, s32_2, 8);
 
-    // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #16
+    // CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #16
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#16|#0x10}}
+    // CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
     result = __SXTAB16_RORn(s32_1, s32_2, 16);
 
-    // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24
+    // CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24
+    // CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#24|#0x18}}
+    // CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
     result = __SXTAB16_RORn(s32_1, s32_2, 24);
 
-    // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
-    // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-THUMB: ror{{s?}}.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-ARM: ror{{s?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
     // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, [[REG]]
     // CHECK-NOT: , ror
     result = __SXTAB16_RORn(s32_1, s32_2, 5);
 
     // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
-    // CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK-NOT: , ror
     result = __SXTAB16_RORn(s32_1, s32_2, u8);
diff --git a/CMSIS/Core/Test/vcpkg-configuration.json b/CMSIS/Core/Test/vcpkg-configuration.json
index 9683cb659..d36396ec1 100644
--- a/CMSIS/Core/Test/vcpkg-configuration.json
+++ b/CMSIS/Core/Test/vcpkg-configuration.json
@@ -9,6 +9,7 @@
     "requires": {
         "arm:compilers/arm/armclang": "6.23.0",
         "arm:compilers/arm/arm-none-eabi-gcc": "14.2.1",
-        "arm:compilers/arm/llvm-embedded": "20.1.0"
+        "arm:compilers/arm/llvm-embedded": "20.1.0",
+        "arm:compilers/iar/cxarm": "9.70.1"
     }
 }
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py
index 41f654839..3d69b8aa6 100755
--- a/CMSIS/CoreValidation/Project/build.py
+++ b/CMSIS/CoreValidation/Project/build.py
@@ -82,7 +82,7 @@ def image_ext(self):
         ext = {
             CompilerAxis.AC6: 'axf',
             CompilerAxis.GCC: 'elf',
-            CompilerAxis.IAR: 'elf',
+            CompilerAxis.IAR: 'out',
             CompilerAxis.CLANG: 'elf',
         }
         return ext[self]
@@ -286,11 +286,6 @@ def qemu_exec(config):
     return cmdline
 
 
-@matrix_filter
-def filter_iar(config):
-    return config.compiler == CompilerAxis.IAR
-
-
 @matrix_filter
 def filter_gcc_cm52(config):
     device = config.device.match('CM52*')
diff --git a/CMSIS/CoreValidation/Project/vcpkg-configuration.json b/CMSIS/CoreValidation/Project/vcpkg-configuration.json
index 7a0287f16..df169e933 100644
--- a/CMSIS/CoreValidation/Project/vcpkg-configuration.json
+++ b/CMSIS/CoreValidation/Project/vcpkg-configuration.json
@@ -7,12 +7,13 @@
         }
     ],
     "requires": {
-        "arm:tools/kitware/cmake": "3.28.4",
+        "arm:tools/kitware/cmake": "3.31.5",
         "arm:compilers/arm/armclang": "6.23.0",
         "arm:compilers/arm/arm-none-eabi-gcc": "14.2.1",
         "arm:compilers/arm/llvm-embedded": "20.1.0",
+        "arm:compilers/iar/cxarm": "9.70.1",
         "arm:tools/open-cmsis-pack/cmsis-toolbox": "2.10.0",
         "arm:models/arm/avh-fvp": "11.27.31",
         "arm:tools/ninja-build/ninja": "1.12.0"
     }
-}
\ No newline at end of file
+}
diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md
index 0c0eea5c4..488d2c81d 100644
--- a/CMSIS/CoreValidation/README.md
+++ b/CMSIS/CoreValidation/README.md
@@ -20,6 +20,7 @@ Currently, the following build configurations are provided:
    - Arm Compiler 6 (AC6)
    - GNU Compiler (GCC)
    - LLVM/Clang (Clang)
+   - IAR Toolchain (IAR)
 2. Devices
    - Cortex-M0
    - Cortex-M0+
@@ -68,6 +69,7 @@ The following tools are required to build and run the CoreValidation tests:
 - [Arm Compiler 6.20](https://artifacts.keil.arm.com/arm-compiler/6.20/21/)*
 - [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)*
 - [Clang Compiler 17.0.1](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)*
+- [IAR Toolchain 9.70.1](https://github.com/iarsystems/arm/releases/tag/9.70.1)*
 - [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)*
 - [Python 3.9](https://www.python.org/downloads/)