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feat: Provide a wrapper class to expose cpu::CpuPool2d
Resolves: MLINFSW-852 Signed-off-by: Zhibo Li <[email protected]> Change-Id: Ic9dc22094bc06b805634bb6601320d9c581e0e90 Signed-off-by: Zhibo Li <[email protected]> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/13392 Benchmark: Arm Jenkins <[email protected]> Tested-by: Arm Jenkins <[email protected]> Comments-Addressed: Arm Jenkins <[email protected]> Reviewed-by: Gunes Bayir <[email protected]>
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‎Android.bp‎

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@@ -1005,6 +1005,7 @@ cc_library_static {
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"src/runtime/experimental/operators/CpuGemmDirectConv2d.cpp",
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"src/runtime/experimental/operators/CpuMeanStdDevNormalization.cpp",
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"src/runtime/experimental/operators/CpuMul.cpp",
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"src/runtime/experimental/operators/CpuPool2d.cpp",
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"src/runtime/experimental/operators/CpuQuantize.cpp",
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"src/runtime/experimental/operators/CpuSoftmax.cpp",
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"src/runtime/experimental/operators/CpuSub.cpp",

‎arm_compute/runtime/experimental/operators/CpuPool2d.h‎

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/*
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* Copyright (c) 2017-2020, 2024-2025 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef ACL_ARM_COMPUTE_RUNTIME_EXPERIMENTAL_OPERATORS_CPUPOOL2D_H
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#define ACL_ARM_COMPUTE_RUNTIME_EXPERIMENTAL_OPERATORS_CPUPOOL2D_H
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#include "arm_compute/core/TensorInfo.h"
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#include "arm_compute/core/Types.h" // required for PoolingLayerInfo
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#include "arm_compute/runtime/NEON/INEOperator.h"
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#include <memory>
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namespace arm_compute
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{
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namespace experimental
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{
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namespace op
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{
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/*
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* A shallow wrapper for arm_compute::cpu::CpuPool2d.
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* Any new features should be added to arm_compute::cpu::CpuPool2d,
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* and arm_compute::experimental::op::CpuPool2d should remain a shallow wrapper.
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* Note this is not thread safe therefore no thread safety tests provided.
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*/
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class CpuPool2d : public INEOperator
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{
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public:
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/** Constructor **/
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CpuPool2d();
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/** Prevent instances of this class from being copied (As this class contains pointers) **/
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CpuPool2d(const CpuPool2d &) = delete;
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/** Prevent copy assignment **/
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CpuPool2d &operator=(const CpuPool2d &) = delete;
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/** Default move constructor **/
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CpuPool2d(CpuPool2d &&) = default;
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/** Default move assignment **/
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CpuPool2d &operator=(CpuPool2d &&) = default;
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/** Default destructor **/
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~CpuPool2d() override;
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/** Set the src and dst tensors.
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*
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* Valid data layouts:
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* - NHWC
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* - NCHW
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*
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* Valid data type configurations:
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* |src |dst |
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* |:--------------|:--------------|
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* |QASYMM8 |QASYMM8 |
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* |QASYMM8_SIGNED |QASYMM8_SIGNED |
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* |F16 |F16 |
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* |F32 |F32 |
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*
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* @note F16 is supported for pool sizes 2 and 3 only
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* @note Source tensor is padded with -inf for MAX pooling and 0 otherwise
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* Cases where pooling region is completely outside input tensor are only supported for floating point data type
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*
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* @param[in, out] src Source tensor info. (Written to only when padding != 0) Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
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* @param[out] dst Destination tensor info. Data types supported: same as @p src.
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* @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo.
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* @param[out] indices (optional) The indices of the maximal values. Data type supported: U32.
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*/
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void
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configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &pool_info, ITensorInfo *indices = nullptr);
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/** Static function to check if given info will lead to a valid configuration
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*
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* Similar to @ref CpuPool2d::configure()
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*/
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static Status validate(const ITensorInfo *src,
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const ITensorInfo *dst,
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const PoolingLayerInfo &pool_info,
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const ITensorInfo *indices = nullptr);
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// Inherited methods overridden:
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void run(ITensorPack &tensors) override;
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experimental::MemoryRequirements workspace() const override;
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private:
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struct Impl;
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std::unique_ptr<Impl> impl_;
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};
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} // namespace op
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} //namespace experimental
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} // namespace arm_compute
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#endif // ACL_ARM_COMPUTE_RUNTIME_EXPERIMENTAL_OPERATORS_CPUPOOL2D_H

‎filelist.json‎

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"src/runtime/experimental/operators/CpuMul.cpp",
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"src/runtime/experimental/operators/CpuQuantize.cpp",
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"src/runtime/experimental/operators/CpuSoftmax.cpp",
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"src/runtime/experimental/operators/CpuPool2d.cpp",
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"src/runtime/experimental/operators/CpuSub.cpp",
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"src/runtime/experimental/operators/CpuTranspose.cpp",
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"src/runtime/experimental/operators/CpuWinogradConv2d.cpp"

‎src/BUILD.bazel‎

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"runtime/experimental/operators/CpuGemmDirectConv2d.cpp",
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"runtime/experimental/operators/CpuMeanStdDevNormalization.cpp",
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"runtime/experimental/operators/CpuMul.cpp",
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"runtime/experimental/operators/CpuPool2d.cpp",
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"runtime/experimental/operators/CpuQuantize.cpp",
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"runtime/experimental/operators/CpuSoftmax.cpp",
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"runtime/experimental/operators/CpuSub.cpp",

‎src/CMakeLists.txt‎

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runtime/experimental/operators/CpuGemmDirectConv2d.cpp
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runtime/experimental/operators/CpuMeanStdDevNormalization.cpp
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runtime/experimental/operators/CpuMul.cpp
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runtime/experimental/operators/CpuPool2d.cpp
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runtime/experimental/operators/CpuQuantize.cpp
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runtime/experimental/operators/CpuSoftmax.cpp
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runtime/experimental/operators/CpuSub.cpp

‎src/runtime/experimental/operators/CpuPool2d.cpp‎

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/*
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* Copyright (c) 2025 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "arm_compute/runtime/experimental/operators/CpuPool2d.h"
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#include "src/cpu/operators/CpuPool2d.h"
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namespace arm_compute
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{
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namespace experimental
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{
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namespace op
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{
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struct CpuPool2d::Impl
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{
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std::unique_ptr<arm_compute::cpu::CpuPool2d> op{nullptr};
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};
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CpuPool2d::CpuPool2d() : impl_(std::make_unique<Impl>())
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{
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impl_->op = std::make_unique<cpu::CpuPool2d>();
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}
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CpuPool2d::~CpuPool2d() = default;
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void CpuPool2d::configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &pool_info, ITensorInfo *indices)
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{
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impl_->op->configure(src, dst, pool_info, indices);
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}
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Status CpuPool2d::validate(const ITensorInfo *src,
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const ITensorInfo *dst,
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const PoolingLayerInfo &pool_info,
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const ITensorInfo *indices)
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{
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return cpu::CpuPool2d::validate(src, dst, pool_info, indices);
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}
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void CpuPool2d::run(ITensorPack &tensors)
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{
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impl_->op->run(tensors);
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}
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experimental::MemoryRequirements CpuPool2d::workspace() const
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{
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return impl_->op->workspace();
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}
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} //namespace op
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} //namespace experimental
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} //namespace arm_compute

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