@@ -188,7 +188,7 @@ index c57825949c1c..12db2ab1fca2 100644
188188 return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
189189 Alignment.value(), RTLIB::MEMCPY);
190190
191- + if (Subtarget.UseInlineMemcpyAsLdSt )
191+ + if (Subtarget.allowInlineMemcpyAsLdSt() )
192192+ return EmitMemcpyAsLdSt(DAG, dl, Subtarget, Chain, Dst, Src, SizeVal,
193193+ isVolatile, DstPtrInfo, SrcPtrInfo);
194194+
@@ -212,6 +212,19 @@ index 275b1c0f8dc0..6ff422c15b12 100644
212212 SDValue
213213 EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
214214 SDValue Dst, SDValue Src, SDValue Size,
215+ diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
216+ index 2f7af05a259f..0acf919b1360 100644
217+ --- a/llvm/lib/Target/ARM/ARMSubtarget.h
218+ +++ b/llvm/lib/Target/ARM/ARMSubtarget.h
219+ @@ -523,6 +523,8 @@ public:
220+ bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
221+ unsigned PhysReg) const override;
222+ unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
223+ +
224+ + bool allowInlineMemcpyAsLdSt() const { return UseInlineMemcpyAsLdSt; }
225+ };
226+
227+ } // end namespace llvm
215228- -
2162292.34.1
217230
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