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@nasherm nasherm commented Oct 31, 2024

Performance improvements have been seen of around 1 to 2% on selected benchmarks when LDM/STM inlining is disabled for Cortex m7. This adds a patch file that enables this optimisation.

Performance improvements have been seen of around 1 to 2%
on selected benchmarks when LDM/STM inlining is disabled for
Cortex m7. This adds a patch file that enables this optimisation.

Change-Id: I5d2cdcfc76a24c7cfbe63a6ca5fe9ea00e1d1fda
@nasherm nasherm changed the title Disable MEMCPY LDM/STM inlining for Cortex m7 Patch file to disable MEMCPY LDM/STM inlining for Cortex m7 Oct 31, 2024
Change-Id: Ibc46465918ca0cfe0f07eaad5f689ddbf1c10fc1
Change-Id: I214c8cbe9d26e11d0a728f28141938d32e64d213
@nasherm nasherm force-pushed the nashe/memcpy-inlining-v7 branch from 475c280 to 4a5467b Compare November 1, 2024 11:53
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LGTM

@nasherm nasherm changed the title Patch file to disable MEMCPY LDM/STM inlining for Cortex m7 Patch file for alternative MEMCPY LDM/STM inlining for Cortex m7 Nov 4, 2024
@nasherm nasherm merged commit cd41a86 into main Nov 4, 2024
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3 participants