@@ -467,6 +467,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
467467* Added feature test macro for FEAT_CSSC.
468468* Added support for modal 8-bit floating point matrix multiply-accumulate widening intrinsics.
469469* Added support for 16-bit floating point matrix multiply-accumulate widening intrinsics.
470+ * Removed all references to Transactional Memory Extension (TME)
470471
471472### References
472473
@@ -1769,13 +1770,6 @@ the Armv8.1-A [[ARMARMv81]](#ARMARMv81) architecture are supported on this targe
17691770Note: It is strongly recommended that standardized C11/C++11 atomics are used to
17701771implement atomic operations in user code.
17711772
1772- ### Transactional Memory Extension
1773-
1774- `__ARM_FEATURE_TME` is defined to `1` if the Transactional Memory
1775- Extension instructions are supported in hardware and intrinsics defined
1776- in [Transactional Memory Extension (TME)
1777- intrinsics](#transactional-memory-extension-tme-intrinsics) are available.
1778-
17791773### Armv8.7-A Load/Store 64 Byte extension
17801774
17811775`__ARM_FEATURE_LS64` is defined to 1 if the Armv8.7-A `LD64B`,
@@ -14486,40 +14480,6 @@ The MVE load and store instructions provide for alignment assertions, which may
1448614480speed up access to aligned data (and will fault access to unaligned data). The
1448714481MVE intrinsics do not directly provide a means for asserting alignment.
1448814482
14489- # Transactional Memory Extension (TME) intrinsics
14490-
14491- ## Introduction
14492-
14493- This section describes the intrinsics for the instructions of the
14494- Transactional Memory Extension (TME). TME adds support for transactional
14495- execution where transactions are started and
14496- committed by a set of new instructions. The TME instructions are present
14497- in the AArch64 execution state only.
14498-
14499- TME is designed to improve performance in cases where larger system scaling
14500- requires atomic and isolated access to data structures whose composition is
14501- dynamic in nature and therefore not readily amenable to fine-grained locking
14502- or lock-free approaches.
14503-
14504- TME transactions are *isolated*. This means that transactional stores are
14505- hidden from other observers, and transactional loads cannot see stores from
14506- other observers until the transaction commits. Also, if the transaction fails
14507- then stores to memory and writes to registers by the transaction are discarded
14508- and the processor returns to the state it had when the transaction started.
14509-
14510- TME transactions are *best-effort*. This means that the architecture does not
14511- guarantee success for any transaction. The architecture requires that all
14512- transactions specify a failure handler allowing the software to fallback to a
14513- non-transactional alternative to provide guarantees of forward progress.
14514-
14515- TME defines *flattened nesting* of transactions, where nested transactions are
14516- subsumed by the outer transaction. This means that the effects of a nested
14517- transaction do not become visible to other observers until the outer
14518- transaction commits. When a nested transaction fails it causes the
14519- outer transaction, and all nested transactions within, to fail.
14520-
14521- The TME intrinsics are available when `__ARM_FEATURE_TME` is defined.
14522-
1452314483## Failure definitions
1452414484
1452514485Transactions can fail due to various causes. The following macros
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