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| 1 | +/* |
| 2 | + * Copyright (c) 2024 Arm Limited. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: MIT |
| 5 | + * |
| 6 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | + * of this software and associated documentation files (the "Software"), to |
| 8 | + * deal in the Software without restriction, including without limitation the |
| 9 | + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | + * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | + * furnished to do so, subject to the following conditions: |
| 12 | + * |
| 13 | + * The above copyright notice and this permission notice shall be included in all |
| 14 | + * copies or substantial portions of the Software. |
| 15 | + * |
| 16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | + * SOFTWARE. |
| 23 | + */ |
| 24 | + |
| 25 | +/** |
| 26 | + * @file |
| 27 | + * |
| 28 | + * Hardware counters clock extents header. |
| 29 | + */ |
| 30 | + |
| 31 | +#pragma once |
| 32 | + |
| 33 | +#include <device/hwcnt/features.hpp> |
| 34 | + |
| 35 | +#include <array> |
| 36 | +#include <cassert> |
| 37 | +#include <cstddef> |
| 38 | +#include <iterator> |
| 39 | +#include <map> |
| 40 | +#include <type_traits> |
| 41 | +#include <vector> |
| 42 | + |
| 43 | +namespace hwcpipe { |
| 44 | +namespace device { |
| 45 | +namespace hwcnt { |
| 46 | + |
| 47 | +/** |
| 48 | + * Clocks extents class. |
| 49 | + * |
| 50 | + * Stores information about clock numbers and clock names |
| 51 | + */ |
| 52 | +class clock_extents { |
| 53 | + public: |
| 54 | + /** Number of clock types. GPU Cycle Clock and SC Cycle Clock */ |
| 55 | + static const constexpr size_t num_clock_types = 2; |
| 56 | + |
| 57 | + using num_clock_types_strings_type = std::array<const char *, num_clock_types>; |
| 58 | + |
| 59 | + /** |
| 60 | + * Construct clock extents. |
| 61 | + * |
| 62 | + * @param[in] has_gpu_cycle does GPU support GPU clock |
| 63 | + * @param[in] has_sc_cycle does GPU support SC clock |
| 64 | + */ |
| 65 | + clock_extents(bool has_gpu_cycle, bool has_sc_cycle) { |
| 66 | + was_set = true; |
| 67 | + has_gpu_cycle_ = false; |
| 68 | + has_sc_cycle_ = false; |
| 69 | + |
| 70 | + if (has_gpu_cycle) { |
| 71 | + has_gpu_cycle_ = true; |
| 72 | + } |
| 73 | + if (has_sc_cycle) { |
| 74 | + has_sc_cycle_ = true; |
| 75 | + } |
| 76 | + } |
| 77 | + |
| 78 | + /** Default ctor. */ |
| 79 | + clock_extents() |
| 80 | + : has_gpu_cycle_(false) |
| 81 | + , has_sc_cycle_(false) |
| 82 | + , was_set(false){}; |
| 83 | + /** Default copy ctor. */ |
| 84 | + clock_extents(const clock_extents &) = default; |
| 85 | + /** Default assign. */ |
| 86 | + clock_extents &operator=(const clock_extents &) = default; |
| 87 | + |
| 88 | + /** @return number of clocks. */ |
| 89 | + uint16_t num_of_enabled_clocks() const { return static_cast<uint16_t>(has_gpu_cycle_ + has_sc_cycle_); } |
| 90 | + |
| 91 | + /** @return is GPU cycle clock enabled. */ |
| 92 | + bool has_gpu_cycle() const { return has_gpu_cycle_; } |
| 93 | + |
| 94 | + /** @return is Shader cycle clock enabled. */ |
| 95 | + bool has_sc_cycle() const { return has_sc_cycle_; } |
| 96 | + |
| 97 | + bool was_clock_extent_set() const { return was_set; } |
| 98 | + |
| 99 | + /** @return clock names in domain order */ |
| 100 | + const std::vector<const char *> get_active_clock_strings() const { |
| 101 | + std::vector<const char *> ret; |
| 102 | + if (has_gpu_cycle_) |
| 103 | + ret.push_back(clock_types_strings[gpu_cycle_idx]); |
| 104 | + if (has_sc_cycle_) |
| 105 | + ret.push_back(clock_types_strings[sc_cycle_idx]); |
| 106 | + return ret; |
| 107 | + }; |
| 108 | + |
| 109 | + private: |
| 110 | + bool has_gpu_cycle_; |
| 111 | + bool has_sc_cycle_; |
| 112 | + bool was_set; |
| 113 | + static constexpr size_t gpu_cycle_idx = 0; |
| 114 | + static constexpr size_t sc_cycle_idx = 1; |
| 115 | + |
| 116 | + static const constexpr num_clock_types_strings_type clock_types_strings = { |
| 117 | + "Top cycle", |
| 118 | + "Shader cores", |
| 119 | + }; |
| 120 | +}; |
| 121 | + |
| 122 | +} // namespace hwcnt |
| 123 | +} // namespace device |
| 124 | +} // namespace hwcpipe |
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