@@ -319,6 +319,17 @@ uint32_t GetClockFreq (uint32_t clk_src);
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uint32_t SystemCoreClock = 120000000U ; /* System Clock Frequency (Core Clock) */
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+ /*----------------------------------------------------------------------------
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+ Approximate delay function (must be used after SystemCoreClockUpdate() call)
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+ *----------------------------------------------------------------------------*/
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+ static void WaitUs (uint32_t us , uint32_t clock_hz )
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+ {
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+ us *= (clock_hz / 1000000 ) / 3 ;
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+
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+ while (us -- );
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+ }
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+
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+
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#define PLL0_NSEL_MAX (1<<8)
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/* pre-divider: compute ndec from nsel */
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static unsigned ndec_new (unsigned nsel )
@@ -417,7 +428,7 @@ static void SetClock (void) {
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(0 << 2 ) ; /* Low-frequency mode */
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/* Wait ~250us @ 12MHz */
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- for ( i = 1500 ; i ; i -- );
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+ WaitUs ( 250 , CLK_XTAL );
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#ifdef USE_SPIFI
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/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
@@ -456,8 +467,8 @@ static void SetClock (void) {
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LPC_CGU -> BASE_M4_CLK = (0x01 << 11 ) | /* Autoblock En */
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(0x09 << 24 ) ; /* Clock source: PLL1 */
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- /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
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- for ( i = 1050 ; i ; i -- ); /* Wait minimum 2100 cycles */
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+ /* Wait 20us */
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+ WaitUs ( 20 , ( CLK_XTAL * ( PLL1_MSEL + 1 )) / (( PLL1_NSEL + 1 ) * 2 ));
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#endif
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/* Configure PLL1 */
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LPC_CGU -> PLL1_CTRL = (0 << 0 ) | /* PLL1 Enabled */
@@ -547,17 +558,6 @@ static void SetClock (void) {
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}
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- /*----------------------------------------------------------------------------
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- Approximate delay function (must be used after SystemCoreClockUpdate() call)
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- *----------------------------------------------------------------------------*/
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- #define CPU_NANOSEC (x ) (((uint64_t)(x) * SystemCoreClock)/1000000000)
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-
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- static void WaitUs (uint32_t us ) {
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- uint32_t cyc = us * CPU_NANOSEC (1000 )/4 ;
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- while (cyc -- );
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- }
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-
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-
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/*----------------------------------------------------------------------------
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Measure frequency using frequency monitor
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*----------------------------------------------------------------------------*/
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