lpc43xx_hic: use pll1 in direct mode

Author: Adrian Negreanu

source/hic_hal/nxp/lpc4322/system_LPC43xx.c

@@ -161,11 +161,11 @@
 
 /* PLL1 output clock: 120MHz, Fcco: 240MHz, N = 1, M = 20, P = 1              */
 #define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
-#define PLL1_MSEL  19           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_MSEL   9           /* Range [0 - 255]: Feedback-divider ratio M  */
 #define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
 
 #define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
-#define PLL1_DIRECT 0           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
 #define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
                                 /* 1: FCLKOUT is used as PLL feedback         */