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Commit 33e07fc

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author
Kyle Wenner
committed
Removed commented code, parenthesis move to same line, remove dbg statements
1 parent ca72613 commit 33e07fc

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1 file changed

+101
-153
lines changed

1 file changed

+101
-153
lines changed

‎source/family/ambiq/ama3b1kk/target_reset.c‎

Lines changed: 101 additions & 153 deletions
Original file line numberDiff line numberDiff line change
@@ -45,198 +45,146 @@
4545

4646
uint8_t swd_set_state_ama3b1kk(target_state_t state)
4747
{
48-
uint32_t val, scratch0, secure; //jdecpid, bootldr
48+
uint32_t val, scratch0, secure, jdecpid, bootldr;
4949
int8_t ap_retries = 2;
5050
swd_init();
51-
switch (state)
52-
{
53-
case RESET_HOLD:
54-
debug_msg("swd_set_state_ama3b1kk RESET_HOLD \r\n");
55-
swd_set_target_reset(1);
56-
break;
57-
58-
case RESET_RUN:
59-
debug_msg("swd_set_state_ama3b1kk RESET_RUN \r\n");
60-
swd_set_target_reset(1);
61-
osDelay(2);
62-
swd_set_target_reset(0);
63-
osDelay(2);
64-
swd_off();
65-
break;
66-
67-
case RESET_PROGRAM:
68-
debug_msg("swd_set_state_ama3b1kk RESET_PROGRAM \r\n");
69-
if (!swd_init_debug())
70-
{
71-
debug_msg("if (!swd_init_debug()) \r\n");
72-
return 0;
73-
}
74-
75-
// Enable debug and halt the core (DHCSR <- 0xA05F0003)
76-
while (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT) == 0)
77-
{
78-
if (--ap_retries <= 0)
79-
{
80-
debug_msg("if (--ap_retries <= 0) \r\n");
81-
return 0;
82-
}
83-
// Target is in invalid state?
51+
switch (state) {
52+
case RESET_HOLD:
53+
swd_set_target_reset(1);
54+
break;
55+
56+
case RESET_RUN:
8457
swd_set_target_reset(1);
8558
osDelay(2);
8659
swd_set_target_reset(0);
8760
osDelay(2);
88-
}
89-
90-
// Wait until core is halted
91-
do
92-
{
93-
if (!swd_read_word(DBG_HCSR, &val))
94-
{
95-
debug_msg("if (!swd_read_word(DBG_HCSR, &val)) 160\r\n");
61+
swd_off();
62+
break;
63+
64+
case RESET_PROGRAM:
65+
if (!swd_init_debug()) {
9666
return 0;
9767
}
98-
} while ((val & S_HALT) == 0);
99-
100-
// Enable halt on reset
101-
//Confirm it is an apollo3
102-
// if (!swd_read_word(JDEC_PID, &jdecpid))
103-
// {
104-
// return 0;
105-
// }
106-
// if ((jdecpid & 0xf0) == 0xc0)
107-
// {
108-
// if (!swd_read_word(MCUCTRL_BOOTLDR, &bootldr))
109-
// {
110-
// return 0;
111-
// }
112-
secure = true; //((bootldr & 0x0C000000) == 0x04000000);
113-
// }
114-
115-
if (secure)
116-
{
117-
if (!swd_read_word(MCUCTRL_SCRATCH0, &scratch0))
118-
{
119-
debug_msg(" if (!swd_read_word(MCUCTRL_SCRATCH0, &scratch0)) \r\n");
68+
69+
// Enable debug and halt the core (DHCSR <- 0xA05F0003)
70+
while (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT) == 0) {
71+
if (--ap_retries <= 0) {
12072
return 0;
73+
}
74+
// Target is in invalid state?
75+
swd_set_target_reset(1);
76+
osDelay(2);
77+
swd_set_target_reset(0);
78+
osDelay(2);
12179
}
122-
if (!swd_write_word(MCUCTRL_SCRATCH0, (scratch0 | 0x1)))
123-
{
124-
debug_msg("if (!swd_write_word(MCUCTRL_SCRATCH0, (scratch0 | 0x1))) \r\n");
80+
81+
// Wait until core is halted
82+
do {
83+
if (!swd_read_word(DBG_HCSR, &val)) {
84+
return 0;
85+
}
86+
} while ((val & S_HALT) == 0);
87+
88+
// Enable halt on reset
89+
//Confirm it is an apollo3
90+
if (!swd_read_word(JDEC_PID, &jdecpid)) {
12591
return 0;
12692
}
127-
}
128-
else
129-
{
130-
if (!swd_write_word(DBG_EMCR, VC_CORERESET))
131-
{
132-
debug_msg("if (!swd_write_word(DBG_EMCR, VC_CORERESET)) \r\n");
133-
return 0;
93+
if ((jdecpid & 0xf0) == 0xc0) {
94+
if (!swd_read_word(MCUCTRL_BOOTLDR, &bootldr)) {
95+
return 0;
96+
}
97+
secure = ((bootldr & 0x0C000000) == 0x04000000);
13498
}
135-
}
13699

137-
// Perform a soft reset
138-
if (!swd_read_word(NVIC_AIRCR, &val))
139-
{
140-
debug_msg("if (!swd_read_word(NVIC_AIRCR, &val)) \r\n");
141-
return 0;
142-
}
143-
144-
if (!swd_write_word(NVIC_AIRCR, VECTKEY | (val & SCB_AIRCR_PRIGROUP_Msk) | SYSRESETREQ))
145-
{
146-
debug_msg("if (!swd_write_word(NVIC_AIRCR, VECTKEY | (val & SCB_AIRCR_PRIGROUP_Msk) | SYSRESETREQ)) \r\n");
147-
return 0;
148-
}
149-
150-
osDelay(10);
100+
if (secure) {
101+
if (!swd_read_word(MCUCTRL_SCRATCH0, &scratch0)) {
102+
return 0;
103+
}
104+
if (!swd_write_word(MCUCTRL_SCRATCH0, (scratch0 | 0x1))) {
105+
return 0;
106+
}
107+
} else {
108+
if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
109+
return 0;
110+
}
111+
}
151112

152-
do
153-
{
154-
if (!swd_read_word(DBG_HCSR, &val))
155-
{
156-
debug_msg("if (!swd_read_word(DBG_HCSR, &val)) 221\r\n");
113+
// Perform a soft reset
114+
if (!swd_read_word(NVIC_AIRCR, &val)) {
157115
return 0;
158116
}
159-
} while ((val & S_HALT) == 0);
160-
161-
// Disable halt on reset
162-
if (secure)
163-
{
164-
if (!swd_write_word(MCUCTRL_SCRATCH0, scratch0))
165-
{
166-
debug_msg("if (!swd_write_word(MCUCTRL_SCRATCH0, scratch0)) \r\n");
117+
118+
if (!swd_write_word(NVIC_AIRCR, VECTKEY | (val & SCB_AIRCR_PRIGROUP_Msk) | SYSRESETREQ)) {
167119
return 0;
168120
}
169-
}
170-
else
171-
{
172-
if (!swd_write_word(DBG_EMCR, 0))
173-
{
174-
debug_msg("if (!swd_write_word(DBG_EMCR, 0)) \r\n");
175-
return 0;
121+
122+
osDelay(10);
123+
124+
do {
125+
if (!swd_read_word(DBG_HCSR, &val)) {
126+
return 0;
127+
}
128+
} while ((val & S_HALT) == 0);
129+
130+
// Disable halt on reset
131+
if (secure) {
132+
if (!swd_write_word(MCUCTRL_SCRATCH0, scratch0)) {
133+
return 0;
134+
}
135+
} else {
136+
if (!swd_write_word(DBG_EMCR, 0)) {
137+
return 0;
138+
}
176139
}
177-
}
178140

179-
break;
141+
break;
180142

181-
case NO_DEBUG:
182-
debug_msg("swd_set_state_ama3b1kk NO_DEBUG \r\n");
183-
if (!swd_write_word(DBG_HCSR, DBGKEY))
184-
{
185-
return 0;
186-
}
143+
case NO_DEBUG:
144+
if (!swd_write_word(DBG_HCSR, DBGKEY)) {
145+
return 0;
146+
}
187147

188-
break;
148+
break;
189149

190-
case DEBUG:
191-
debug_msg("swd_set_state_ama3b1kk DEBUG \r\n");
192-
if (!JTAG2SWD())
193-
{
194-
return 0;
195-
}
150+
case DEBUG:
151+
if (!JTAG2SWD()) {
152+
return 0;
153+
}
196154

197-
if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR))
198-
{
199-
return 0;
200-
}
155+
if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
156+
return 0;
157+
}
201158

202-
// Ensure CTRL/STAT register selected in DPBANKSEL
203-
if (!swd_write_dp(DP_SELECT, 0))
204-
{
205-
return 0;
206-
}
159+
// Ensure CTRL/STAT register selected in DPBANKSEL
160+
if (!swd_write_dp(DP_SELECT, 0)) {
161+
return 0;
162+
}
207163

208-
// Power up
209-
if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ))
210-
{
211-
return 0;
212-
}
164+
// Power up
165+
if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
166+
return 0;
167+
}
213168

214-
// Enable debug
215-
if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN))
216-
{
217-
return 0;
218-
}
169+
// Enable debug
170+
if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
171+
return 0;
172+
}
219173

220-
break;
174+
break;
221175

222-
default:
223-
return 0;
176+
default:
177+
return 0;
224178
}
225179

226180
return 1;
227181
}
228182

229183
const target_family_descriptor_t g_ambiq_ama3b1kk = {
230184
.family_id = kAmbiq_ama3b1kk_FamilyID,
231-
//.default_reset_type = kHardwareReset,
232185
.default_reset_type = kSoftwareReset,
233186
.soft_reset_type = SYSRESETREQ,
234-
//.target_before_init_debug = target_before_init_debug,
235-
//.target_unlock_sequence = target_unlock_sequence,
236-
//.target_set_state = target_set_state,
237-
//.security_bits_set = security_bits_set,
238-
//.swd_set_target_reset = swd_set_target_reset_ama3b1kk,
239187
.target_set_state = swd_set_state_ama3b1kk,
240188
};
241189

242-
//const target_family_descriptor_t *g_target_family = &_g_target_family;
190+

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