lpc4322 (core): set CGU to use 120 MHz core clock

Author: mbrossard

docs/hic/README.md

@@ -7,7 +7,7 @@
 | [kl26z](kl26z.md)             |  M0+ |  48 Mhz |  16 KB | 128 KB |  FS |
 | [kl27z](kl27z.md)             |  M0+ |  48 Mhz |  32 KB | 128 KB |  FS |
 | [lpc11u35](lpc11u35.md)       |  M0  |  48 Mhz |  12 KB |  64 KB |  FS |
-| [lpc4322](lpc4322.md)         |  M4  |  96 MHz | 256 KB | 256 KB |  HS |
+| [lpc4322](lpc4322.md)         |  M4  | 120 MHz | 256 KB | 256 KB |  HS |
 | [lpc55xx](lpc55xx.md)         |  M33 | 150 MHz | 272 KB | 320 KB |  HS |
 | [max32625](max32625.md)       |  M4  |  96 MHz | 160 KB | 512 KB |  FS |
 | [nrf52820](nrf52820.md)       |  M4  |  64 MHz |  32 KB | 256 KB |  FS |

docs/hic/lpc4322.md

@@ -1,7 +1,7 @@
 # lpc4322 HIC
 
 Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC435X_3X_2X_1X.pdf)):
-- Cortex-M4 204 Mhz
+- Cortex-M4 204 Mhz (currently run at 120 MHz)
 - 512 KB Flash
 - 104 KB RAM
 - High-speed USB 2.0 device controller
@@ -16,7 +16,7 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee
 
 Bootloader size is 64 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|

records/hic_hal/lpc4322.yaml

@@ -8,7 +8,7 @@ common:
         - CORE_M4
         - INTERNAL_FLASH
         - DAPLINK_HIC_ID=0x97969905  # DAPLINK_HIC_ID_LPC4322
-        - OS_CLOCK=96000000
+        - OS_CLOCK=120000000
     includes:
         - source/hic_hal/nxp/lpc4322
         - source/hic_hal/nxp/lpc4322/RTE_Driver

source/hic_hal/nxp/lpc4322/board_LPC43xx.c

@@ -24,8 +24,8 @@
 
 void sdk_init(void)
 {
-    /* Set core clock to 96MHz */
-    CGU_Init(96000000);
+    /* Set core clock to 120MHz */
+    CGU_Init(120000000);
     /* Set up USB0 clock */
     /* Disable PLL first */
     CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE);

source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c

@@ -244,7 +244,7 @@ uint32_t	CGU_Init(uint32_t wantedFreq)
     // Setup PLL1 to 204MHz
     // 0. Select IRC as BASE_M4_CLK source
     CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4);
-    SystemCoreClock = 96000000;
+    SystemCoreClock = 120000000;
     // 1. Enable the crystal oscillator
     CGU_SetXTALOSC(12000000);
     CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);