Skip to content

Commit d2992f4

Browse files
committed
lpc4322 (SWO): configure UART1 for SWO, enable SWO for LPC55S69-EVK board
1 parent dac348d commit d2992f4

File tree

4 files changed

+16
-12
lines changed

4 files changed

+16
-12
lines changed

records/board/lpc55S69xpresso.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
11
common:
2+
macros:
3+
- SWO_UART=1
24
sources:
35
board:
46
- source/board/lpc55S69xpresso.c

records/hic_hal/lpc4322.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,11 @@ common:
1111
- OS_CLOCK=96000000
1212
includes:
1313
- source/hic_hal/nxp/lpc4322
14+
- source/hic_hal/nxp/lpc4322/RTE_Driver
1415
sources:
1516
hic_hal:
1617
- source/hic_hal/nxp/lpc4322
18+
- source/hic_hal/nxp/lpc4322/RTE_Driver
1719

1820
tool_specific:
1921
uvision:

source/hic_hal/nxp/lpc4322/DAP_config.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ typedef unsigned int BOOL;
9797
/// This configuration settings is used to optimize the communication performance with the
9898
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
9999
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
100-
#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
100+
#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
101101

102102
/// Indicate that UART Serial Wire Output (SWO) trace is available.
103103
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
@@ -106,7 +106,7 @@ typedef unsigned int BOOL;
106106
#endif
107107

108108
/// USART Driver instance number for the UART SWO.
109-
#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
109+
#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
110110

111111
/// Maximum SWO UART Baudrate
112112
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz

source/hic_hal/nxp/lpc4322/RTE_Device.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
/* --------------------------------------------------------------------------
2-
* Copyright (c) 2013-2016 Arm Limited (or its affiliates). All
1+
/* --------------------------------------------------------------------------
2+
* Copyright (c) 2013-2016 Arm Limited (or its affiliates). All
33
* rights reserved.
44
*
55
* SPDX-License-Identifier: Apache-2.0
@@ -1125,12 +1125,12 @@
11251125
// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
11261126

11271127
// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
1128-
#define RTE_UART1 0
1128+
#define RTE_UART1 1
11291129

11301130
// <h> Pin Configuration
11311131
// <o> TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11
11321132
// <i> UART0 Serial Output pin
1133-
#define RTE_UART1_TX_ID 2
1133+
#define RTE_UART1_TX_ID 0
11341134
#if (RTE_UART1_TX_ID == 0)
11351135
#define RTE_UART1_TX_PIN_EN 0
11361136
#elif (RTE_UART1_TX_ID == 1)
@@ -1193,7 +1193,7 @@
11931193

11941194
// <h> Modem Lines
11951195
// <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
1196-
#define RTE_UART1_CTS_ID 1
1196+
#define RTE_UART1_CTS_ID 0
11971197
#if (RTE_UART1_CTS_ID == 0)
11981198
#define RTE_UART1_CTS_PIN_EN 0
11991199
#elif (RTE_UART1_CTS_ID == 1)
@@ -1219,7 +1219,7 @@
12191219
#define RTE_UART1_CTS_PIN_EN 1
12201220
#endif
12211221
// <o> RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5
1222-
#define RTE_UART1_RTS_ID 1
1222+
#define RTE_UART1_RTS_ID 0
12231223
#if (RTE_UART1_RTS_ID == 0)
12241224
#define RTE_UART1_RTS_PIN_EN 0
12251225
#elif (RTE_UART1_RTS_ID == 1)
@@ -1245,7 +1245,7 @@
12451245
#define RTE_UART1_RTS_PIN_EN 1
12461246
#endif
12471247
// <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
1248-
#define RTE_UART1_DCD_ID 1
1248+
#define RTE_UART1_DCD_ID 0
12491249
#if (RTE_UART1_DCD_ID == 0)
12501250
#define RTE_UART1_DCD_PIN_EN 0
12511251
#elif (RTE_UART1_DCD_ID == 1)
@@ -1271,7 +1271,7 @@
12711271
#define RTE_UART1_DCD_PIN_EN 1
12721272
#endif
12731273
// <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
1274-
#define RTE_UART1_DSR_ID 1
1274+
#define RTE_UART1_DSR_ID 0
12751275
#if (RTE_UART1_DSR_ID == 0)
12761276
#define RTE_UART1_DSR_PIN_EN 0
12771277
#elif (RTE_UART1_DSR_ID == 1)
@@ -1297,7 +1297,7 @@
12971297
#define RTE_UART1_DSR_PIN_EN 1
12981298
#endif
12991299
// <o> DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10
1300-
#define RTE_UART1_DTR_ID 1
1300+
#define RTE_UART1_DTR_ID 0
13011301
#if (RTE_UART1_DTR_ID == 0)
13021302
#define RTE_UART1_DTR_PIN_EN 0
13031303
#elif (RTE_UART1_DTR_ID == 1)
@@ -1323,7 +1323,7 @@
13231323
#define RTE_UART1_DTR_PIN_EN 1
13241324
#endif
13251325
// <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
1326-
#define RTE_UART1_RI_ID 1
1326+
#define RTE_UART1_RI_ID 0
13271327
#if (RTE_UART1_RI_ID == 0)
13281328
#define RTE_UART1_RI_PIN_EN 0
13291329
#elif (RTE_UART1_RI_ID == 1)

0 commit comments

Comments
 (0)