hic_docs: document the number of endpoints for each HIC

mbrossard · mbrossard · commit df8e414ffa44 · 2022-01-08T02:00:28.000-06:00
diff --git a/docs/hic/k20dx.md b/docs/hic/k20dx.md
@@ -4,9 +4,11 @@ Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 - Cortex-M4 50 Mhz
 - 160 KB Flash
 - 16 KB RAM
-- Full-speed USB 2.0 OTG controller
+- Full-speed USB 2.0 OTG controller: up to 16 bi-directional endpoints including EP0 (*)
 - HVQFN32 packaging
 
+(*) "16 bidirectional endpoints can be supported" (source: [K20P32M50SF0RM :lock:](https://www.nxp.com/webapp/Download?colCode=K20P32M50SF0RM))
+
 ## Memory Map
 
 | Region   |   Size | Start       | End         |
@@ -16,7 +18,7 @@ Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 
 Bootloader size is 32 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/k26f.md b/docs/hic/k26f.md
@@ -4,9 +4,11 @@ Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee
 - Cortex-M4 180 Mhz
 - 2 MB Flash
 - 256 KB RAM
-- High-speed USB 2.0 OTG controller
+- High-speed USB 2.0 OTG controller (USBHS): up to 8 bi-directional endpoints including EP0 (**)
 - LFBGA169 packaging
 
+(*) "Supports eight programmable, bidirectional USB endpoints, including endpoint 0" (source [K26P169M180SF5RM :lock:](https://www.nxp.com/webapp/Download?colCode=K26P169M180SF5RM))
+
 ## Memory Map
 
 | Region   |   Size | Start       | End         |
@@ -16,7 +18,7 @@ Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee
 
 Bootloader size is 64 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/kl26z.md b/docs/hic/kl26z.md
@@ -4,9 +4,11 @@ Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 - Cortex-M0+ 48 Mhz
 - 128 KB Flash
 - 16 KB RAM
-- Full-speed USB 2.0 OTG controller
+- Full-speed USB 2.0 OTG controller: up to 16 bi-directional endpoints including EP0 (*)
 - HVQFN32 packaging
 
+(*) "16 bidirectional endpoints can be supported" (source: [KL26P121M48SF4RM :lock:](https://www.nxp.com/webapp/Download?colCode=KL26P121M48SF4RM))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
@@ -16,7 +18,7 @@ Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 
 Bootloader size is 32 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/kl27z.md b/docs/hic/kl27z.md
@@ -4,9 +4,11 @@ Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 - Cortex-M0+ 48 Mhz
 - 256 KB Flash
 - 32 KB RAM
-- Full-speed USB 2.0 device controller
+- Full-speed USB 2.0 device controller: up to 16 bi-directional endpoints including EP0 (*)
 - HVQFN32 packaging
 
+(*) "16 bidirectional endpoints can be supported" (source: [KL27P64M48SF6RM :lock:](https://www.nxp.com/webapp/Download?colCode=KL27P64M48SF6RM))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
@@ -16,7 +18,7 @@ Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet
 
 Bootloader size is 32 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/lpc11u35.md b/docs/hic/lpc11u35.md
@@ -4,9 +4,11 @@ Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-s
 - Cortex-M0 48 Mhz
 - 64 KB Flash
 - 12 KB RAM
-- Full-speed USB 2.0 device controller
+- Full-speed USB 2.0 device controller: 5 bi-directional endpoints including EP0(*)
 - HVQFN32 packaging
 
+(*) "Supports 10 physical (5 logical) endpoints including one control endpoint" (source: [Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC11U3X.pdf))
+
 ## Memory Map
 
 | Region   |  Size | Start       | End         |
@@ -18,7 +20,7 @@ Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-s
 
 Because of the flash size limitation, the presence of a ROM USB loader (also Cortex-M0 does not support vector table relocation).
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md
@@ -4,9 +4,12 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee
 - Cortex-M4 204 Mhz (currently run at 120 MHz)
 - 512 KB Flash
 - 104 KB RAM
-- High-speed USB 2.0 device controller
+- High-speed USB 2.0 device controller: 6 bi-directional endpoints including EP0 (*)
 - TFBGA100 packaging
 
+(*) : "Supports six logical endpoints including one control endpoint for a total of 12 physical
+endpoints." (source: [UM10503 :lock:](https://www.nxp.com/webapp/Download?colCode=UM10503))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md
@@ -1,15 +1,17 @@
 # lpc55xx HIC
 
-Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC55S6x.pdf)):
+Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf)):
 - Cortex-M33 150 Mhz (cores)
 - 640 KB Flash
 - 320 KB RAM
-- High-speed USB 2.0 host/device controller
+- High-speed USB 2.0 host/device controller: 8 bi-directional endpoints including EP0 (*)
 - HTQFP64 packaging
 
 In order to support other MCUs from the LPC5500 family, the HIC limits usage
 to one core, 256 KB Flash and 96 KB RAM.
 
+(*) "Supports 8 physical (16 logical) endpoints" (source: [Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
diff --git a/docs/hic/max32625.md b/docs/hic/max32625.md
@@ -4,9 +4,12 @@ Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/
 - Cortex-M4 96 Mhz
 - 512 KB Flash
 - 160 KB RAM
-- Full-speed USB 2.0 device controller
+- Full-speed USB 2.0 device controller: up to 7 uni-directional endpoints excluding EP0 (*)
 - 63 WLP packaging
 
+(*) "A total of 7 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0."
+(source: [AN6350](https://pdfserv.maximintegrated.com/en/an/AN6350.pdf))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
@@ -16,7 +19,7 @@ Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/
 
 Bootloader size is 64 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 Reference design is based on [MAX32625PICO](https://www.maximintegrated.com/en/products/microcontrollers/MAX32625PICO.html).
 
diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md
@@ -5,9 +5,11 @@ and [nRF52833](https://www.nordicsemi.com/Products/nRF52833):
 - Cortex-M4 64 MHz
 - 256 KB Flash
 - 32 KB RAM
-- Full-speed USB 2.0 device controller
+- Full-speed USB 2.0 device controller: up to 9 bi-directional endpoints including EP0 (*)
 - QFN40 packaging
 
+(*) "Endpoints: 2 control (1 IN, 1 OUT) [...] 14 bulk/interrupt (7 IN, 7 OUT) [...] 2 isochronous (1 IN, 1 OUT)" (source: [Datasheet](https://infocenter.nordicsemi.com/pdf/nRF52820_OPS_v0.7.pdf))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md
@@ -4,9 +4,11 @@ Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/Devi
 - Cortex-M3 96 Mhz
 - 128 KB Flash
 - 36 KB RAM
-- High-speed USB 2.0 device controller
+- High-speed USB 2.0 device controller: up to 7 bi-directional endpoints including EP0 (*)
 - LQFP100 packaging
 
+(*) "up to 7 bidirectional Endpoints" (source: Datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6430-32-bit-Cortex-M3-Microcontroller-SAM3U4-SAM3U2-SAM3U1_Datasheet.pdf))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
@@ -16,7 +18,7 @@ Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/Devi
 
 Bootloader size is 32 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
diff --git a/docs/hic/stm32f103xb.md b/docs/hic/stm32f103xb.md
@@ -4,9 +4,11 @@ Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datashee
 - Cortex-M3 72 Mhz
 - 128 KB Flash
 - 20 KB RAM
-- Full-speed USB 2.0 device controller
+- Full-speed USB 2.0 device controller: up to 8 bi-directional endpoints including EP0 (*)
 - UFQFPN48 packaging
 
+(*) "Configurable number of endpoints from 1 to 8", "up to 16 mono-directional or 8 bidirectional endpoints can be used". (source: [RM0008](https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf))
+
 ## Memory Map
 
 | Region   |  Size  | Start       | End         |
@@ -16,7 +18,7 @@ Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datashee
 
 Bootloader size is 48 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|
