@@ -781,33 +781,44 @@ int QSPIFBlockDevice::_sfdp_set_qpi_enabled(uint8_t *basic_param_table_ptr)
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switch (en_seq_444_value) {
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case 1 :
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case 2 :
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- tr_debug (" _setQPIEnabled - send command 38h" );
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- _qspi_send_general_command (0x38 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , NULL , 0 );
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+ tr_debug (" _sfdp_set_qpi_enabled - send command 38h" );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x38 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , NULL , 0 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - send command 38h Failed" );
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+ }
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break ;
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case 4 :
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- tr_debug (" _setQPIEnabled - send command 35h" );
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- _qspi_send_general_command (0x35 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , NULL , 0 );
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+ tr_debug (" _sfdp_set_qpi_enabled - send command 35h" );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x35 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , NULL , 0 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - send command 35h Failed" );
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+ }
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break ;
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case 8 :
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- tr_debug (" _setQPIEnabled - set config bit 6 and send command 71h" );
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- _qspi_send_general_command (0x65 , 0x800003 , NULL , 0 , (char *)config_reg, 1 );
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+ tr_debug (" _sfdp_set_qpi_enabled - set config bit 6 and send command 71h" );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x65 , 0x800003 , NULL , 0 , (char *)config_reg, 1 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - set config bit 6 command 65h Failed" );
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+ }
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config_reg[0 ] |= 0x40 ; // Set Bit 6
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- _qspi_send_general_command (0x71 , 0x800003 , NULL , 0 , (char *)config_reg, 1 );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x71 , 0x800003 , NULL , 0 , (char *)config_reg, 1 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - send command 71h Failed" );
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+ }
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break ;
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case 16 :
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- tr_debug (" DEBUG: _setQPIEnabled - reset config bits 0-7 and send command 61h" );
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- _qspi_send_general_command (0x65 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , (char *)config_reg, 1 );
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+ tr_debug (" _sfdp_set_qpi_enabled - reset config bits 0-7 and send command 61h" );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x65 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , (char *)config_reg, 1 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - send command 65h Failed" );
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+ }
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config_reg[0 ] &= 0x7F ; // Reset Bit 7 of CR
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- _qspi_send_general_command (0x61 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , (char *)config_reg, 1 );
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+ if (QSPI_STATUS_OK != _qspi_send_general_command (0x61 , QSPI_NO_ADDRESS_COMMAND, NULL , 0 , (char *)config_reg, 1 )) {
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+ tr_error (" _sfdp_set_qpi_enabled - send command 61 Failed" );
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+ }
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break ;
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default :
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- tr_warning (" _setQPIEnabled - Unsuported En Seq 444 configuration" );
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+ tr_warning (" _sfdp_set_qpi_enabled - Unsuported En Seq 444 configuration" );
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break ;
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-
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}
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return 0 ;
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}
@@ -1087,7 +1098,7 @@ int QSPIFBlockDevice::_reset_flash_mem()
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QSPI_MAX_STATUS_REGISTER_SIZE) ) { // store received values in status_value
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tr_debug (" Reading Status Register Success: value = 0x%x" , (int )status_value[0 ]);
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} else {
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- tr_debug (" Reading Status Register failed: value = 0x%x" , (int )status_value[0 ]);
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+ tr_error (" Reading Status Register failed: value = 0x%x" , (int )status_value[0 ]);
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status = -1 ;
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}
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