A fix to enum issue

Author: Archcady

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h

@@ -60,12 +60,13 @@ extern u32 CfgSysDebugWarn;
 #define _DBG_MISC_              0x40000000
 #define	_DBG_FAULT_        	    0x80000000
 
-typedef enum _SYSTEM_DBG_DEFINE_ {
+enum _SYSTEM_DBG_DEFINE_ {
     _SYSDBG_MISC_       = 1<<0,
     _SYSDBG_MAILBOX_    = 1<<1,
     _SYSDBG_TIMER_      = 1<<2
 
-} SYSTEM_DBG;
+}; 
+typedef uint32_t SYSTEM_DBG;
 
 extern
 _LONG_CALL_ROM_ u32
@@ -826,11 +827,12 @@ prvDiagSPrintf(
 #define IDENT_EIGHT_SPACE  "        "
 
 #ifdef CONFIG_DEBUG_LOG
-typedef enum _DBG_CFG_TYPE_ {
+enum _DBG_CFG_TYPE_ {
 	DBG_CFG_ERR=0,
 	DBG_CFG_WARN=1,
 	DBG_CFG_INFO=2
-} DBG_CFG_TYPE;
+};
+typedef uint32_t DBG_CFG_TYPE;
 
 typedef struct _DBG_CFG_CMD_ {
 	u8 cmd_name[16];
@@ -839,9 +841,10 @@ typedef struct _DBG_CFG_CMD_ {
 
 #endif
 
-typedef enum _CONSOLE_OP_STAGE_ {
+enum _CONSOLE_OP_STAGE_ {
     ROM_STAGE = 0,
     RAM_STAGE = 1
-}CONSOLE_OP_STAGE;
+};
+typedef uint32_t CONSOLE_OP_STAGE;
 
 #endif //_DIAG_H_

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h

@@ -321,7 +321,7 @@
 #define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
 #define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
 
-typedef enum _GDMA_CHANNEL_NUM_ {
+enum _GDMA_CHANNEL_NUM_ {
         GdmaNoCh    = 0x0000,
         GdmaCh0     = 0x0101,
         GdmaCh1     = 0x0202,
@@ -332,35 +332,45 @@ typedef enum _GDMA_CHANNEL_NUM_ {
         GdmaCh6     = 0x4040,
         GdmaCh7     = 0x8080,
         GdmaAllCh   = 0xffff
-}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
+};
+typedef uint32_t GDMA_CHANNEL_NUM;
+typedef uint32_t *PGDMA_CHANNEL_NUM;
 
 
 //3 CTL register struct
 
-typedef enum _GDMA_CTL_TT_FC_TYPE_ {
+enum _GDMA_CTL_TT_FC_TYPE_ {
         TTFCMemToMem    = 0x00,
         TTFCMemToPeri   = 0x01,
         TTFCPeriToMem   = 0x02
-}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
+};
+typedef uint32_t GDMA_CTL_TT_FC_TYPE;
+typedef uint32_t *PGDMA_CTL_TT_FC_TYPE;
 
 //Max type = Bus Width
-typedef enum _GDMA_CTL_TR_WIDTH_ {
+enum _GDMA_CTL_TR_WIDTH_ {
         TrWidthOneByte    = 0x00,
         TrWidthTwoBytes   = 0x01,
         TrWidthFourBytes  = 0x02
-}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
+};
+typedef uint32_t GDMA_CTL_TR_WIDTH;
+typedef uint32_t *PGDMA_CTL_TR_WIDTH;
 
-typedef enum _GDMA_CTL_MSIZE_ {
+enum _GDMA_CTL_MSIZE_ {
         MsizeOne        = 0x00,
         MsizeFour       = 0x01,
         MsizeEight      = 0x02
-}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
+};
+typedef uint32_t GDMA_CTL_MSIZE;
+typedef uint32_t *PGDMA_CTL_MSIZE;
 
-typedef enum _GDMA_INC_TYPE_ {
+enum _GDMA_INC_TYPE_ {
         IncType         = 0x00,
         DecType         = 0x01,
         NoChange        = 0x02
-}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
+};
+typedef uint32_t GDMA_INC_TYPE;
+typedef uint32_t *PGDMA_INC_TYPE;
 
 
 typedef struct _GDMA_CTL_REG_ {
@@ -386,7 +396,7 @@ typedef struct _GDMA_CTL_REG_ {
 
 //3 CFG Register Structure
 
-typedef enum _GDMA_CH_PRIORITY_ {
+enum _GDMA_CH_PRIORITY_ {
     Prior0          = 0,
     Prior1          = 1,
     Prior2          = 2,
@@ -395,13 +405,17 @@ typedef enum _GDMA_CH_PRIORITY_ {
     Prior5          = 5,
     Prior6          = 6,
     Prior7          = 7
-}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
+};
+typedef uint32_t GDMA_CH_PRIORITY;
+typedef uint32_t *PGDMA_CH_PRIORITY;
 
-typedef enum _GDMA_LOCK_LEVEL_ {
+enum _GDMA_LOCK_LEVEL_ {
     OverComplDmaTransfer        = 0x00,
     OverComplDmaBlockTransfer   = 0x01,
     OverComplDmaTransation      = 0x02
-}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
+};
+typedef uint32_t GDMA_LOCK_LEVEL;
+typedef uint32_t *PGDMA_LOCK_LEVEL;
 
 
 typedef struct _GDMA_CFG_REG_ {
@@ -427,13 +441,15 @@ typedef struct _GDMA_CFG_REG_ {
     u16                     Rsvd13To15  :3;
 }GDMA_CFG_REG, *PGDMA_CFG_REG;
 
-typedef enum _GDMA_ISR_TYPE_ {
+enum _GDMA_ISR_TYPE_ {
     TransferType        = 0x1,
     BlockType           = 0x2,
     SrcTransferType     = 0x4,
     DstTransferType     = 0x8,
     ErrType             = 0x10
-}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
+};
+typedef uint32_t GDMA_ISR_TYPE;
+typedef uint32_t *PGDMA_ISR_TYPE;
 
 
 VOID

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h

@@ -790,17 +790,21 @@
 //======================================================
 // I2C related enumeration
 // I2C Address Mode
-typedef enum _I2C_ADDR_MODE_   {
+enum _I2C_ADDR_MODE_   {
     I2C_ADDR_7BIT   =   0,
     I2C_ADDR_10BIT  =   1,  
-}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
+};
+typedef uint32_t I2C_ADDR_MODE;
+typedef uint32_t *PI2C_ADDR_MODE;
 
 // I2C Speed Mode
-typedef enum _I2C_SPD_MODE_   {
+enum _I2C_SPD_MODE_   {
     I2C_SS_MODE     =   1,
     I2C_FS_MODE     =   2,
     I2C_HS_MODE     =   3,
-}I2C_SPD_MODE,*PI2C_SPD_MODE;
+};
+typedef uint32_t I2C_SPD_MODE;
+typedef uint32_t *PI2C_SPD_MODE;
 
 //I2C Timing Parameters
 #define I2C_SS_MIN_SCL_HTIME    4000    //the unit is ns.

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h

@@ -326,46 +326,60 @@
 
 
 // SSI Pinmux Select
-typedef enum _SSI0_PINMUX_SELECT_ {
+enum _SSI0_PINMUX_SELECT_ {
     SSI0_MUX_TO_GPIOE = S0,
     SSI0_MUX_TO_GPIOC = S1
-}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
+};
+typedef uint32_t SSI0_PINMUX_SELECT;
+typedef uint32_t *PSSI0_PINMUX_SELECT;
 
-typedef enum _SSI1_PINMUX_SELECT_ {
+enum _SSI1_PINMUX_SELECT_ {
     SSI1_MUX_TO_GPIOA = S0,
     SSI1_MUX_TO_GPIOB = S1,
     SSI1_MUX_TO_GPIOD = S2
-}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
+};
+typedef uint32_t SSI1_PINMUX_SELECT;
+typedef uint32_t *PSSI1_PINMUX_SELECT;
 
-typedef enum _SSI2_PINMUX_SELECT_ {
+enum _SSI2_PINMUX_SELECT_ {
     SSI2_MUX_TO_GPIOG = S0,
     SSI2_MUX_TO_GPIOE = S1,
     SSI2_MUX_TO_GPIOD = S2
-}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
+};
+typedef uint32_t SSI2_PINMUX_SELECT;
+typedef uint32_t *PSSI2_PINMUX_SELECT;
 
-typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
+enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
     SSI0_CS_MUX_TO_GPIOE    = S0,
     SSI0_CS_MUX_TO_GPIOC    = S1
-}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
+};
+typedef uint32_t SSI0_MULTI_CS_PINMUX_SELECT;
+typedef uint32_t *PSSI0_MULTI_CS_PINMUX_SELECT;
 
-typedef enum _SSI_CTRLR0_TMOD_ {
+enum _SSI_CTRLR0_TMOD_ {
     TMOD_TR       = 0,
     TMOD_TO       = 1,
     TMOD_RO       = 2,
     TMOD_EEPROM_R = 3
-}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
+};
+typedef uint32_t SSI_CTRLR0_TMOD;
+typedef uint32_t *PSSI_CTRLR0_TMOD;
 
-typedef enum _SSI_CTRLR0_SCPOL_ {
+enum _SSI_CTRLR0_SCPOL_ {
     SCPOL_INACTIVE_IS_LOW  = 0,
     SCPOL_INACTIVE_IS_HIGH = 1
-}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
+};
+typedef uint32_t SSI_CTRLR0_SCPOL;
+typedef uint32_t *PSSI_CTRLR0_SCPOL;
 
-typedef enum _SSI_CTRLR0_SCPH_ {
+enum _SSI_CTRLR0_SCPH_ {
     SCPH_TOGGLES_IN_MIDDLE = 0,
     SCPH_TOGGLES_AT_START  = 1
-}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
+};
+typedef uint32_t SSI_CTRLR0_SCPH;
+typedef uint32_t *PSSI_CTRLR0_SCPH;
 
-typedef enum _SSI_CTRLR0_DFS_ {
+enum _SSI_CTRLR0_DFS_ {
     DFS_4_BITS   = 3,
     DFS_5_BITS   = 4,
     DFS_6_BITS   = 5,
@@ -379,9 +393,11 @@ typedef enum _SSI_CTRLR0_DFS_ {
     DFS_14_BITS  = 13,
     DFS_15_BITS  = 14,
     DFS_16_BITS  = 15,
-}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
+};
+typedef uint32_t SSI_CTRLR0_DFS;
+typedef uint32_t *PSSI_CTRLR0_DFS;
 
-typedef enum _SSI_CTRLR0_CFS_ {
+enum _SSI_CTRLR0_CFS_ {
     CFS_1_BIT    = 0,
     CFS_2_BITS   = 1,
     CFS_3_BITS   = 2,
@@ -398,52 +414,70 @@ typedef enum _SSI_CTRLR0_CFS_ {
     CFS_14_BITS  = 13,
     CFS_15_BITS  = 14,
     CFS_16_BITS  = 15
-}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
+};
+typedef uint32_t SSI_CTRLR0_CFS;
+typedef uint32_t *PSSI_CTRLR0_CFS;
 
-typedef enum _SSI_CTRLR0_SLV_OE_ {
+enum _SSI_CTRLR0_SLV_OE_ {
     SLV_TXD_ENABLE  = 0,
     SLV_TXD_DISABLE = 1
-}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
+};
+typedef uint32_t SSI_CTRLR0_SLV_OE;
+typedef uint32_t *PSSI_CTRLR0_SLV_OE;
 
-typedef enum _SSI_ROLE_SELECT_ {
+enum _SSI_ROLE_SELECT_ {
     SSI_SLAVE  = 0,
     SSI_MASTER = 1
-}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
+};
+typedef uint32_t SSI_ROLE_SELECT;
+typedef uint32_t *PSSI_ROLE_SELECT;
 
-typedef enum _SSI_FRAME_FORMAT_ {
+enum _SSI_FRAME_FORMAT_ {
     FRF_MOTOROLA_SPI = 0,
     FRF_TI_SSP       = 1,
     FRF_NS_MICROWIRE = 2,
     FRF_RSVD         = 3
-}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
+};
+typedef uint32_t SSI_FRAME_FORMAT;
+typedef uint32_t *PSSI_FRAME_FORMAT;
 
-typedef enum _SSI_DMACR_ENABLE_ {
+enum _SSI_DMACR_ENABLE_ {
     SSI_NODMA        = 0,
     SSI_RXDMA_ENABLE = 1,
     SSI_TXDMA_ENABLE = 2,
     SSI_TRDMA_ENABLE = 3
-}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
+};
+typedef uint32_t SSI_DMACR_ENABLE;
+typedef uint32_t *PSSI_DMACR_ENABLE;
 
-typedef enum _SSI_MWCR_HANDSHAKE_ {
+enum _SSI_MWCR_HANDSHAKE_ {
     MW_HANDSHAKE_DISABLE = 0,
     MW_HANDSHAKE_ENABLE  = 1
-}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
+};
+typedef uint32_t SSI_MWCR_HANDSHAKE;
+typedef uint32_t *PSSI_MWCR_HANDSHAKE;
 
-typedef enum _SSI_MWCR_DIRECTION_ {
+enum _SSI_MWCR_DIRECTION_ {
     MW_DIRECTION_SLAVE_TO_MASTER = 0,
     MW_DIRECTION_MASTER_TO_SLAVE = 1
-}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
+};
+typedef uint32_t SSI_MWCR_DIRECTION;
+typedef uint32_t *PSSI_MWCR_DIRECTION;
 
-typedef enum _SSI_MWCR_TMOD_ {
+enum _SSI_MWCR_TMOD_ {
     MW_TMOD_NONSEQUENTIAL = 0,
     MW_TMOD_SEQUENTIAL    = 1
-}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
+};
+typedef uint32_t SSI_MWCR_TMOD;
+typedef uint32_t *PSSI_MWCR_TMOD;
 
-typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
+enum _SSI_DATA_TRANSFER_MECHANISM_ {
     SSI_DTM_BASIC,
     SSI_DTM_INTERRUPT,
     SSI_DTM_DMA
-}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
+};
+typedef uint32_t SSI_DATA_TRANSFER_MECHANISM;
+typedef uint32_t *PSSI_DATA_TRANSFER_MECHANISM;
 
 
 _LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);