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Merge pull request #12069 from jeromecoutant/PR_ASTYLE
STM32: astyle update
2 parents 0c227a0 + bea83d0 commit 06da499

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20 files changed

+922
-1036
lines changed

20 files changed

+922
-1036
lines changed

‎features/mbedtls/targets/TARGET_STM/TARGET_STM32F7/aes_alt.c

Lines changed: 192 additions & 182 deletions
Large diffs are not rendered by default.

‎features/mbedtls/targets/TARGET_STM/TARGET_STM32F7/aes_alt.h

Lines changed: 21 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,7 @@ mbedtls_aes_context;
7373
/**
7474
* \brief The AES XTS context-type definition.
7575
*/
76-
typedef struct mbedtls_aes_xts_context
77-
{
76+
typedef struct mbedtls_aes_xts_context {
7877
mbedtls_aes_context crypt; /*!< The AES context to use for AES block
7978
encryption or decryption. */
8079
mbedtls_aes_context tweak; /*!< The AES context used for tweak
@@ -105,7 +104,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx);
105104
*
106105
* \param ctx The AES XTS context to initialize. This must not be \c NULL.
107106
*/
108-
void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx );
107+
void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx);
109108

110109
/**
111110
* \brief This function releases and clears the specified AES XTS context.
@@ -114,7 +113,7 @@ void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx );
114113
* If this is \c NULL, this function does nothing.
115114
* Otherwise, the context must have been at least initialized.
116115
*/
117-
void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx );
116+
void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx);
118117
#endif /* MBEDTLS_CIPHER_MODE_XTS */
119118

120119
/**
@@ -158,9 +157,9 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
158157
* \return \c 0 on success.
159158
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
160159
*/
161-
int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
162-
const unsigned char *key,
163-
unsigned int keybits );
160+
int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx,
161+
const unsigned char *key,
162+
unsigned int keybits);
164163

165164
/**
166165
* \brief This function prepares an XTS context for decryption and
@@ -178,9 +177,9 @@ int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
178177
* \return \c 0 on success.
179178
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
180179
*/
181-
int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx,
182-
const unsigned char *key,
183-
unsigned int keybits );
180+
int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx,
181+
const unsigned char *key,
182+
unsigned int keybits);
184183
#endif /* MBEDTLS_CIPHER_MODE_XTS */
185184

186185
/**
@@ -265,12 +264,12 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
265264
* smaller than an AES block in size (16 Bytes) or if \p
266265
* length is larger than 2^20 blocks (16 MiB).
267266
*/
268-
int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
269-
int mode,
270-
size_t length,
271-
const unsigned char data_unit[16],
272-
const unsigned char *input,
273-
unsigned char *output );
267+
int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx,
268+
int mode,
269+
size_t length,
270+
const unsigned char data_unit[16],
271+
const unsigned char *input,
272+
unsigned char *output);
274273
#endif /* MBEDTLS_CIPHER_MODE_XTS */
275274

276275
#if defined(MBEDTLS_CIPHER_MODE_CFB)
@@ -385,12 +384,12 @@ int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
385384
*
386385
* \return \c 0 on success.
387386
*/
388-
int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx,
389-
size_t length,
390-
size_t *iv_off,
391-
unsigned char iv[16],
392-
const unsigned char *input,
393-
unsigned char *output );
387+
int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx,
388+
size_t length,
389+
size_t *iv_off,
390+
unsigned char iv[16],
391+
const unsigned char *input,
392+
unsigned char *output);
394393

395394
#endif /* MBEDTLS_CIPHER_MODE_OFB */
396395

‎features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_DISCO_H747I/stm32h7_eth_init.c

Lines changed: 54 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@
6363
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
6464
{
6565
GPIO_InitTypeDef GPIO_InitStruct;
66-
if(heth->Instance == ETH)
67-
{
66+
if (heth->Instance == ETH) {
6867
/* Disable DCache for STM32H7 family */
6968
SCB_DisableDCache();
7069

@@ -80,37 +79,37 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
8079
__HAL_RCC_ETH1TX_CLK_ENABLE();
8180
__HAL_RCC_ETH1RX_CLK_ENABLE();
8281

83-
/**ETH GPIO Configuration
84-
PG11 ------> ETH_TX_EN
85-
PG12 ------> ETH_TXD1
86-
PG13 ------> ETH_TXD0
87-
PC1 ------> ETH_MDC
88-
PA2 ------> ETH_MDIO
89-
PA1 ------> ETH_REF_CLK
90-
PA7 ------> ETH_CRS_DV
91-
PC4 ------> ETH_RXD0
92-
PC5 ------> ETH_RXD1
93-
*/
94-
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
95-
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
96-
GPIO_InitStruct.Pull = GPIO_NOPULL;
97-
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
98-
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
99-
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
100-
101-
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
102-
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
103-
GPIO_InitStruct.Pull = GPIO_NOPULL;
104-
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
105-
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
106-
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
107-
108-
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
109-
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
110-
GPIO_InitStruct.Pull = GPIO_NOPULL;
111-
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
112-
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
113-
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
82+
/**ETH GPIO Configuration
83+
PG11 ------> ETH_TX_EN
84+
PG12 ------> ETH_TXD1
85+
PG13 ------> ETH_TXD0
86+
PC1 ------> ETH_MDC
87+
PA2 ------> ETH_MDIO
88+
PA1 ------> ETH_REF_CLK
89+
PA7 ------> ETH_CRS_DV
90+
PC4 ------> ETH_RXD0
91+
PC5 ------> ETH_RXD1
92+
*/
93+
GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
94+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
95+
GPIO_InitStruct.Pull = GPIO_NOPULL;
96+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
97+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
98+
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
99+
100+
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
101+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
102+
GPIO_InitStruct.Pull = GPIO_NOPULL;
103+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
104+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
105+
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
106+
107+
GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
108+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
109+
GPIO_InitStruct.Pull = GPIO_NOPULL;
110+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
111+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
112+
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
114113

115114
}
116115
}
@@ -120,29 +119,28 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
120119
*/
121120
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
122121
{
123-
if(heth->Instance == ETH)
124-
{
125-
/* Peripheral clock disable */
126-
__HAL_RCC_ETH1MAC_CLK_DISABLE();
127-
__HAL_RCC_ETH1TX_CLK_DISABLE();
128-
__HAL_RCC_ETH1RX_CLK_DISABLE();
129-
130-
/**ETH GPIO Configuration
131-
PG11 ------> ETH_TX_EN
132-
PG12 ------> ETH_TXD1
133-
PG13 ------> ETH_TXD0
134-
PC1 ------> ETH_MDC
135-
PA2 ------> ETH_MDIO
136-
PA1 ------> ETH_REF_CLK
137-
PA7 ------> ETH_CRS_DV
138-
PC4 ------> ETH_RXD0
139-
PC5 ------> ETH_RXD1
140-
*/
141-
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
142-
143-
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
144-
145-
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
122+
if (heth->Instance == ETH) {
123+
/* Peripheral clock disable */
124+
__HAL_RCC_ETH1MAC_CLK_DISABLE();
125+
__HAL_RCC_ETH1TX_CLK_DISABLE();
126+
__HAL_RCC_ETH1RX_CLK_DISABLE();
127+
128+
/**ETH GPIO Configuration
129+
PG11 ------> ETH_TX_EN
130+
PG12 ------> ETH_TXD1
131+
PG13 ------> ETH_TXD0
132+
PC1 ------> ETH_MDC
133+
PA2 ------> ETH_MDIO
134+
PA1 ------> ETH_REF_CLK
135+
PA7 ------> ETH_CRS_DV
136+
PC4 ------> ETH_RXD0
137+
PC5 ------> ETH_RXD1
138+
*/
139+
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
140+
141+
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
142+
143+
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
146144
}
147145
}
148146

‎features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H743ZI/stm32h7_eth_init.c

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,7 @@
6161
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
6262
{
6363
GPIO_InitTypeDef GPIO_InitStruct;
64-
if(heth->Instance == ETH)
65-
{
64+
if (heth->Instance == ETH) {
6665
/* Disable DCache for STM32H7 family */
6766
SCB_DisableDCache();
6867

@@ -96,14 +95,14 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
9695
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
9796
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
9897

99-
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
98+
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin;
10099
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
101100
GPIO_InitStruct.Pull = GPIO_NOPULL;
102101
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
103102
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
104103
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
105104

106-
GPIO_InitStruct.Pin = RMII_RXD0_Pin|RMII_RXD1_Pin;
105+
GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin;
107106
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
108107
GPIO_InitStruct.Pull = GPIO_NOPULL;
109108
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -117,7 +116,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
117116
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
118117
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
119118

120-
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
119+
GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin;
121120
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
122121
GPIO_InitStruct.Pull = GPIO_NOPULL;
123122
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -131,8 +130,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
131130
*/
132131
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
133132
{
134-
if(heth->Instance == ETH)
135-
{
133+
if (heth->Instance == ETH) {
136134
/* Disable Peripheral clock */
137135
__HAL_RCC_ETH1MAC_CLK_DISABLE();
138136
__HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -149,13 +147,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
149147
PG11 ------> ETH_TX_EN
150148
PG13 ------> ETH_TXD0
151149
*/
152-
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
150+
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin);
153151

154-
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
152+
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin);
155153

156154
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
157155

158-
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
156+
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin);
159157
}
160158
}
161159

‎features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H743ZI2/stm32h7_eth_init.c

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,7 @@
6161
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
6262
{
6363
GPIO_InitTypeDef GPIO_InitStruct;
64-
if(heth->Instance == ETH)
65-
{
64+
if (heth->Instance == ETH) {
6665
/* Disable DCache for STM32H7 family */
6766
SCB_DisableDCache();
6867

@@ -96,14 +95,14 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
9695
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
9796
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
9897

99-
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
98+
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin;
10099
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
101100
GPIO_InitStruct.Pull = GPIO_NOPULL;
102101
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
103102
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
104103
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
105104

106-
GPIO_InitStruct.Pin = RMII_RXD0_Pin|RMII_RXD1_Pin;
105+
GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin;
107106
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
108107
GPIO_InitStruct.Pull = GPIO_NOPULL;
109108
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -117,7 +116,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
117116
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
118117
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
119118

120-
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
119+
GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin;
121120
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
122121
GPIO_InitStruct.Pull = GPIO_NOPULL;
123122
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -131,8 +130,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
131130
*/
132131
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
133132
{
134-
if(heth->Instance == ETH)
135-
{
133+
if (heth->Instance == ETH) {
136134
/* Disable Peripheral clock */
137135
__HAL_RCC_ETH1MAC_CLK_DISABLE();
138136
__HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -149,13 +147,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
149147
PG11 ------> ETH_TX_EN
150148
PG13 ------> ETH_TXD0
151149
*/
152-
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
150+
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin);
153151

154-
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
152+
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin);
155153

156154
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
157155

158-
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
156+
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin);
159157
}
160158
}
161159

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