musca_a1: Add TF-M compatibility

Make the MUSCA_A1 target TF-M compatible by doing the following:
    - Add flash, region definitions, and preprocessed image macros from
      TF-M (at version 6e7be077eabe "Core: Add lifecycle API")
    - Update the MUSCA_A1 linker script to create a flash image
      compatible with TF-M.
    - Update the tfm/bin_utils/assemble.py signing script to work with
      preprocessed image macros rather than flat C pre-processor defines

Signed-off-by: Devaraj Ranganna <[email protected]>
Signed-off-by: Jaeden Amero <[email protected]>

Author: urutva

targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_GCC_ARM/musca_ns.ld

@@ -32,7 +32,7 @@
 
 MEMORY
 {
-  CODE_RAM (rx)  : ORIGIN = NS_CODE_START, LENGTH = ((TOTAL_CODE_SRAM_SIZE / 2) - BL2_HEADER_SIZE)
+  FLASH (rx)  : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
   /* Vector table is copied to RAM, so RAM address needs to be adjusted */
   RAM   (rwx) : ORIGIN = NVIC_RAM_VECTOR_LIMIT, LENGTH = (NS_DATA_SIZE - NVIC_RAM_VECTOR_SIZE)
 }
@@ -46,37 +46,20 @@ ENTRY(Reset_Handler)
 
 SECTIONS
 {
-    /* Startup section is loaded to Flash and runs from Flash */
-    .startup :
+    .text :
     {
         KEEP(*(.vectors))
         __Vectors_End = .;
         __Vectors_Size = __Vectors_End - __Vectors;
         __end__ = .;
 
+        *(.text*)
         KEEP(*(.init))
         KEEP(*(.fini))
 
-    } > CODE_RAM
 
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > CODE_RAM
 
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > CODE_RAM
-    __exidx_end = .;
 
-    /* The text section is loaded into Flash but runs from SRAM
-     * The load address is aligned to 8 bytes
-     */
-    .text : ALIGN(8)
-    {
-        *(.text*)
 
         /* .ctors */
         *crtbegin.o(.ctors)
@@ -95,25 +78,26 @@ SECTIONS
         *(.rodata*)
 
         KEEP(*(.eh_frame*))
-    } >CODE_RAM
-    . = ALIGN(8); /* This alignment is needed to make the section size 8 bytes aligned */
-
-    /* Create same symbols that armclang does so that in the c files
-     * we do not have to deal with the compiler type
-     */
-    Image$$ER_CODE_SRAM$$Base = ADDR(.text);
-    Image$$ER_CODE_SRAM$$Limit = .;
-    Image$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Limit - Image$$ER_CODE_SRAM$$Base;
-    Load$$ER_CODE_SRAM$$Base = LOADADDR(.text);
-    Load$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Length;
-    Load$$ER_CODE_SRAM$$Limit = Load$$ER_CODE_SRAM$$Base + Load$$ER_CODE_SRAM$$Length;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
 
     /* To copy multiple ROM to RAM sections,
      * define etext2/data2_start/data2_end and
      * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_ns.S */
     .copy.table :
     {
-        . = ALIGN(8);
+        . = ALIGN(4);
         __copy_table_start__ = .;
         LONG (__etext)
         LONG (__data_start__)
@@ -122,64 +106,65 @@ SECTIONS
         LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
         LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
         __copy_table_end__ = .;
-    } > CODE_RAM
+    } > FLASH
 
     /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
      * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_ns.S */
     .zero.table :
     {
-        . = ALIGN(8);
+        . = ALIGN(4);
         __zero_table_start__ = .;
         LONG (__bss_start__)
         LONG (__bss_end__ - __bss_start__)
         LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
         LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
         __zero_table_end__ = .;
-    } > CODE_RAM
+    } > FLASH
 
     __etext = .;
 
-    .data : ALIGN(8)
+    .data : AT (__etext)
     {
         __data_start__ = .;
         *(vtable)
         *(.data*)
 
-        . = ALIGN(8);
+        . = ALIGN(4);
         /* preinit data */
         PROVIDE_HIDDEN (__preinit_array_start = .);
         KEEP(*(.preinit_array))
         PROVIDE_HIDDEN (__preinit_array_end = .);
 
-        . = ALIGN(8);
+        . = ALIGN(4);
         /* init data */
         PROVIDE_HIDDEN (__init_array_start = .);
         KEEP(*(SORT(.init_array.*)))
         KEEP(*(.init_array))
         PROVIDE_HIDDEN (__init_array_end = .);
 
 
-        . = ALIGN(8);
+        . = ALIGN(4);
         /* finit data */
         PROVIDE_HIDDEN (__fini_array_start = .);
         KEEP(*(SORT(.fini_array.*)))
         KEEP(*(.fini_array))
         PROVIDE_HIDDEN (__fini_array_end = .);
 
         KEEP(*(.jcr*))
-        . = ALIGN(8);
+        . = ALIGN(4);
         /* All data end */
         __data_end__ = .;
 
-    } > RAM AT>CODE_RAM
+    } > RAM
 
     .bss :
     {
-        . = ALIGN(8);
+        . = ALIGN(4);
         __bss_start__ = .;
         *(.bss*)
         *(COMMON)
-        . = ALIGN(8);
+        . = ALIGN(4);
         __bss_end__ = .;
     } > RAM
 

targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/device_cfg.h

@@ -80,6 +80,6 @@
 #define USEC_REPORTED_FREQ_HZ            (TIMER_FREQ_HZ >> USEC_REPORTED_SHIFT)
 #define USEC_REPORTED_BITS               (32 - USEC_REPORTED_SHIFT)
 
-#define UART_DEFAULT_BAUD_RATE           9600U
+#define DEFAULT_UART_BAUDRATE            9600U
 
 #endif  /* __ARM_LTD_DEVICE_CFG_H__ */