Add support for FRDM K66

Signed-off-by: Mahadevan Mahesh <[email protected]>

Author: mmahadevan108

hal/targets.json

@@ -591,6 +591,19 @@
         "default_build": "standard",
         "release_versions": ["2", "5"]
     },
+    "K66F": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["Freescale", "KSDK2_MCUS", "FRDM"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED", "MBEDTLS_ENTROPY_HARDWARE_ALT"],
+        "inherits": ["Target"],
+        "progen": {"target": "frdm-k66f"},
+        "detect_code": ["0311"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
     "NUCLEO_F030R8": {
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0",

hal/targets/cmsis/TARGET_Freescale/TARGET_K66F/MK66F18.h

@@ -0,0 +1,94 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MK66FN2M0VLQ18
+**                          MK66FN2M0VMD18
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
+**     Version:             rev. 3.0, 2015-03-25
+**     Build:               b151009
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+#define __ram_vector_table__            1
+
+#if (defined(__ram_vector_table__))
+  #define __ram_vector_table_size__    0x00000400
+#else
+  #define __ram_vector_table_size__    0x00000000
+#endif
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_flash_config_start           0x00000400
+#define m_flash_config_size            0x00000010
+
+#define m_text_start                   0x00000410
+#define m_text_size                    0x001FFBF0
+
+#define m_interrupts_ram_start         0x1FFF0000
+#define m_interrupts_ram_size          __ram_vector_table_size__
+
+#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size                    (0x00010000 - m_interrupts_ram_size)
+
+#define m_data_2_start                 0x20000000
+#define m_data_2_size                  0x00030000
+
+
+LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size {   ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address
+    * (FlashConfig)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  RW_IRAM1 m_data_2_start m_data_2_size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {  
+  }
+}