Merge pull request #15099 from jeromecoutant/PR_H723

STM32H7: enable more custom boards

Author: 0xc0170

targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt

@@ -1,9 +1,12 @@
 # Copyright (c) 2020 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
+add_subdirectory(TARGET_STM32H723xG EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32H725xE EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32H743xI EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32H745xI EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32H747xI EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32H750xB EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32H7A3xIQ EXCLUDE_FROM_ALL)
 add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
 

targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h

@@ -69,7 +69,10 @@ typedef enum {
     I2C_1 = (int)I2C1_BASE,
     I2C_2 = (int)I2C2_BASE,
     I2C_3 = (int)I2C3_BASE,
-    I2C_4 = (int)I2C4_BASE
+    I2C_4 = (int)I2C4_BASE,
+#if I2C5_BASE
+    I2C_5 = (int)I2C5_BASE,
+#endif
 } I2CName;
 
 typedef enum {
@@ -81,18 +84,29 @@ typedef enum {
     PWM_3  = (int)TIM3_BASE,
     PWM_4  = (int)TIM4_BASE,
     PWM_5  = (int)TIM5_BASE,
+    PWM_6  = (int)TIM6_BASE,
+    PWM_7  = (int)TIM7_BASE,
     PWM_8  = (int)TIM8_BASE,
     PWM_12 = (int)TIM12_BASE,
     PWM_13 = (int)TIM13_BASE,
     PWM_14 = (int)TIM14_BASE,
     PWM_15 = (int)TIM15_BASE,
     PWM_16 = (int)TIM16_BASE,
-    PWM_17 = (int)TIM17_BASE
+    PWM_17 = (int)TIM17_BASE,
+#if TIM23_BASE
+    PWM_23 = (int)TIM23_BASE,
+#endif
+#if TIM24_BASE
+    PWM_24 = (int)TIM24_BASE,
+#endif
 } PWMName;
 
 typedef enum {
     CAN_1 = (int)FDCAN1_BASE,
-    CAN_2 = (int)FDCAN2_BASE
+    CAN_2 = (int)FDCAN2_BASE,
+#if FDCAN3_BASE
+    CAN_3 = (int)FDCAN3_BASE,
+#endif
 } CANName;
 
 typedef enum {

targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt

@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h723xg.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h723xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32h723xg.sct)
+endif()
+
+add_library(mbed-stm32h723xg INTERFACE)
+
+target_include_directories(mbed-stm32h723xg
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32h723xg
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32h723xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32h723xg INTERFACE mbed-stm32h7)

targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/startup_stm32h723xx.S

@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START  MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE  MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_IRAM1  (MBED_RAM_START + VECTORS_SIZE)  {  ; RW data
+    .ANY (+RW +ZI)
+  }
+
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START + MBED_RAM_SIZE)  EMPTY  -MBED_CONF_TARGET_BOOT_STACK_SIZE  { ; Stack region growing down
+  }
+}