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Fix STM32 SPI async API for STM32H7 (SPI_IP_VERSION_V2)
By default, HAL functions (HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT) assume that SPI is disabled between function invocation. It's needed to set transfer size (CR2 register), that can be modified only if SPI disabled. But `stm32_spi_api.c` keeps SPI enabled after initialization. This commit adds helper code for STM32H7 (SPI_IP_VERSION_V2) that disables SPI before HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT and after end of transaction for HAL API compatibility.
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targets/TARGET_STM/stm_spi_api.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1389,6 +1389,11 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer
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// enable the right hal transfer
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int rc = 0;
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#if defined(SPI_IP_VERSION_V2)
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// HAL SPI API assumes that SPI disabled between transfers and
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// doesn't work properly if SPI is enabled.
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LL_SPI_Disable(SPI_INST(obj));
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#endif
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switch (transfer_type) {
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case SPI_TRANSFER_TYPE_TXRX:
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rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t *)tx, (uint8_t *)rx, words);
@@ -1407,6 +1412,12 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer
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}
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if (rc) {
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#if defined(SPI_IP_VERSION_V2)
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// enable SPI back in case of error
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if (handle->Init.Direction != SPI_DIRECTION_1LINE) {
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LL_SPI_Enable(SPI_INST(obj));
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}
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#endif
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DEBUG_PRINTF("SPI: RC=%u\n", rc);
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length = 0;
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}
@@ -1506,6 +1517,16 @@ inline uint32_t spi_irq_handler_asynch(spi_t *obj)
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*/
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spi_flush_rx(obj);
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}
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#else
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// reset transfer size
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LL_SPI_SetTransferSize(SPI_INST(obj), 0);
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// HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT
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// function disable SPI after transfer. So we need enabled it back,
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// otherwise spi_master_block_write/spi_master_write won't work in 4-wire mode.
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if (handle->Init.Direction != SPI_DIRECTION_1LINE) {
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LL_SPI_Enable(SPI_INST(obj));
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}
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#endif /* SPI_IP_VERSION_V2 */
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}
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