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QSPI: Add explicit pinmap support
1 parent 655a6b8 commit 0cf9b1e

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lines changed

2 files changed

+58
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drivers/QSPI.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,18 @@ class QSPI : private NonCopyable<QSPI> {
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*
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*/
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QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
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/** Create a QSPI master connected to the specified pins
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*
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* io0-io3 is used to specify the Pins used for Quad SPI mode
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*
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* @param pinmap reference to structure which holds static pinmap
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* @param mode Clock polarity and phase mode (0 - 3) of SPI
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* (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
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*
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*/
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QSPI(const qspi_pinmap_t &pinmap, int mode = 0);
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virtual ~QSPI()
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{
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}
@@ -222,13 +234,15 @@ class QSPI : private NonCopyable<QSPI> {
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int _mode; //SPI mode
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bool _initialized;
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PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
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const qspi_pinmap_t *_explicit_pinmap;
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private:
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/* Private acquire function without locking/unlocking
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* Implemented in order to avoid duplicate locking and boost performance
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*/
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bool _acquire(void);
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bool _initialize();
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bool _initialize_direct();
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/*
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* This function builds the qspi command struct to be send to Hal

drivers/source/QSPI.cpp

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
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_qspi_io3 = io3;
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_qspi_clk = sclk;
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_qspi_cs = ssel;
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_explicit_pinmap = NULL;
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_inst_width = QSPI_CFG_BUS_SINGLE;
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_address_width = QSPI_CFG_BUS_SINGLE;
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_address_size = QSPI_CFG_ADDR_SIZE_24;
@@ -65,6 +66,31 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
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MBED_ASSERT(success);
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}
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QSPI::QSPI(const qspi_pinmap_t &pinmap, int mode) : _qspi()
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{
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_qspi_io0 = pinmap.data0_pin;
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_qspi_io1 = pinmap.data1_pin;
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_qspi_io2 = pinmap.data2_pin;
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_qspi_io3 = pinmap.data3_pin;
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_qspi_clk = pinmap.sclk_pin;
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_qspi_cs = pinmap.ssel_pin;
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_explicit_pinmap = &pinmap;
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_inst_width = QSPI_CFG_BUS_SINGLE;
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_address_width = QSPI_CFG_BUS_SINGLE;
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_address_size = QSPI_CFG_ADDR_SIZE_24;
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_alt_width = QSPI_CFG_BUS_SINGLE;
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_alt_size = QSPI_CFG_ALT_SIZE_8;
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_data_width = QSPI_CFG_BUS_SINGLE;
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_num_dummy_cycles = 0;
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_mode = mode;
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_hz = ONE_MHZ;
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_initialized = false;
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//Go ahead init the device here with the default config
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bool success = _initialize_direct();
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MBED_ASSERT(success);
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}
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qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
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{
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// Check that alt_size/alt_width are a valid combination
@@ -255,6 +281,24 @@ bool QSPI::_initialize()
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return _initialized;
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}
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284+
// Note: Private helper function to initialize qspi HAL
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bool QSPI::_initialize_direct()
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{
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if (_mode != 0 && _mode != 1) {
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_initialized = false;
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return _initialized;
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}
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qspi_status_t ret = qspi_init_direct(&_qspi, _explicit_pinmap, _hz, _mode);
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if (QSPI_STATUS_OK == ret) {
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_initialized = true;
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} else {
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_initialized = false;
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}
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return _initialized;
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}
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// Note: Private function with no locking
259303
bool QSPI::_acquire()
260304
{

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