Skip to content

Commit 0edef2d

Browse files
sg-sg-
authored
Merge pull request #2273 from svastm/fix_i2c_clock_l4
[STM32L4XX] Fix i2c clock config
2 parents ff34c5b + 0e63f41 commit 0edef2d

File tree

5 files changed

+75
-83
lines changed

5 files changed

+75
-83
lines changed

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/system_stm32l4xx.c

Lines changed: 9 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -26,43 +26,20 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29+
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30+
* | (external 8 MHz clock) | (internal 16 MHz)
31+
* | 2- PLL_HSE_XTAL | or PLL_MSI
32+
* | (external 8 MHz xtal) | (internal 4 MHz)
2933
*-----------------------------------------------------------------------------
30-
* System Clock source | MSI
34+
* SYSCLK(MHz) | 48 | 80
3135
*-----------------------------------------------------------------------------
32-
* SYSCLK(Hz) | 4000000
36+
* AHBCLK (MHz) | 48 | 80
3337
*-----------------------------------------------------------------------------
34-
* HCLK(Hz) | 4000000
38+
* APB1CLK (MHz) | 48 | 80
3539
*-----------------------------------------------------------------------------
36-
* AHB Prescaler | 1
40+
* APB2CLK (MHz) | 48 | 80
3741
*-----------------------------------------------------------------------------
38-
* APB1 Prescaler | 1
39-
*-----------------------------------------------------------------------------
40-
* APB2 Prescaler | 1
41-
*-----------------------------------------------------------------------------
42-
* PLL_M | 1
43-
*-----------------------------------------------------------------------------
44-
* PLL_N | 8
45-
*-----------------------------------------------------------------------------
46-
* PLL_P | 7
47-
*-----------------------------------------------------------------------------
48-
* PLL_Q | 2
49-
*-----------------------------------------------------------------------------
50-
* PLL_R | 2
51-
*-----------------------------------------------------------------------------
52-
* PLLSAI1_P | NA
53-
*-----------------------------------------------------------------------------
54-
* PLLSAI1_Q | NA
55-
*-----------------------------------------------------------------------------
56-
* PLLSAI1_R | NA
57-
*-----------------------------------------------------------------------------
58-
* PLLSAI2_P | NA
59-
*-----------------------------------------------------------------------------
60-
* PLLSAI2_Q | NA
61-
*-----------------------------------------------------------------------------
62-
* PLLSAI2_R | NA
63-
*-----------------------------------------------------------------------------
64-
* Require 48MHz for USB OTG FS, | Disabled
65-
* SDIO and RNG clock |
42+
* USB capable (48 MHz precise clock) | YES | NO
6643
*-----------------------------------------------------------------------------
6744
*=============================================================================
6845
******************************************************************************

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/system_stm32l4xx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@
4545
******************************************************************************
4646
* @attention
4747
*
48-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
48+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
4949
*
5050
* Redistribution and use in source and binary forms, with or without modification,
5151
* are permitted provided that the following conditions are met:
@@ -205,7 +205,7 @@ void SystemInit(void)
205205
RCC->CR &= (uint32_t)0xEAF6FFFF;
206206

207207
/* Reset PLLCFGR register */
208-
RCC->PLLCFGR = 0x00000800;
208+
RCC->PLLCFGR = 0x00001000;
209209

210210
/* Reset HSEBYP bit */
211211
RCC->CR &= (uint32_t)0xFFFBFFFF;

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/system_stm32l4xx.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,13 @@
22
******************************************************************************
33
* @file system_stm32l4xx.h
44
* @author MCD Application Team
5-
* @version V1.0.0
6-
* @date 26-June-2015
5+
* @version V1.1.1
6+
* @date 29-April-2016
77
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
88
******************************************************************************
99
* @attention
1010
*
11-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
11+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
1212
*
1313
* Redistribution and use in source and binary forms, with or without modification,
1414
* are permitted provided that the following conditions are met:

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c

Lines changed: 9 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -26,43 +26,20 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29+
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30+
* | (external 8 MHz clock) | (internal 16 MHz)
31+
* | 2- PLL_HSE_XTAL | or PLL_MSI
32+
* | (external 8 MHz xtal) | (internal 4 MHz)
2933
*-----------------------------------------------------------------------------
30-
* System Clock source | MSI
34+
* SYSCLK(MHz) | 48 | 80
3135
*-----------------------------------------------------------------------------
32-
* SYSCLK(Hz) | 4000000
36+
* AHBCLK (MHz) | 48 | 80
3337
*-----------------------------------------------------------------------------
34-
* HCLK(Hz) | 4000000
38+
* APB1CLK (MHz) | 48 | 80
3539
*-----------------------------------------------------------------------------
36-
* AHB Prescaler | 1
40+
* APB2CLK (MHz) | 48 | 80
3741
*-----------------------------------------------------------------------------
38-
* APB1 Prescaler | 1
39-
*-----------------------------------------------------------------------------
40-
* APB2 Prescaler | 1
41-
*-----------------------------------------------------------------------------
42-
* PLL_M | 1
43-
*-----------------------------------------------------------------------------
44-
* PLL_N | 8
45-
*-----------------------------------------------------------------------------
46-
* PLL_P | 7
47-
*-----------------------------------------------------------------------------
48-
* PLL_Q | 2
49-
*-----------------------------------------------------------------------------
50-
* PLL_R | 2
51-
*-----------------------------------------------------------------------------
52-
* PLLSAI1_P | NA
53-
*-----------------------------------------------------------------------------
54-
* PLLSAI1_Q | NA
55-
*-----------------------------------------------------------------------------
56-
* PLLSAI1_R | NA
57-
*-----------------------------------------------------------------------------
58-
* PLLSAI2_P | NA
59-
*-----------------------------------------------------------------------------
60-
* PLLSAI2_Q | NA
61-
*-----------------------------------------------------------------------------
62-
* PLLSAI2_R | NA
63-
*-----------------------------------------------------------------------------
64-
* Require 48MHz for USB OTG FS, | Disabled
65-
* SDIO and RNG clock |
42+
* USB capable (48 MHz precise clock) | YES | NO
6643
*-----------------------------------------------------------------------------
6744
*=============================================================================
6845
******************************************************************************

‎hal/targets/hal/TARGET_STM/TARGET_STM32L4/i2c_api.c

Lines changed: 52 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -116,22 +116,60 @@ void i2c_frequency(i2c_t *obj, int hz)
116116
// wait before init
117117
timeout = LONG_TIMEOUT;
118118
while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
119-
120-
// Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0
121-
switch (hz) {
122-
case 100000:
123-
I2cHandle.Init.Timing = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
124-
break;
125-
case 400000:
126-
I2cHandle.Init.Timing = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
127-
break;
128-
case 1000000:
129-
I2cHandle.Init.Timing = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
130-
break;
131-
default:
132-
break;
119+
120+
// Update the SystemCoreClock variable.
121+
SystemCoreClockUpdate();
122+
123+
if (SystemCoreClock == 80000000) {
124+
// Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0
125+
switch (hz) {
126+
case 100000:
127+
I2cHandle.Init.Timing = 0x30C14E6B; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
128+
break;
129+
case 400000:
130+
I2cHandle.Init.Timing = 0x10D1143A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
131+
break;
132+
case 1000000:
133+
I2cHandle.Init.Timing = 0x00810E27; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
134+
break;
135+
default:
136+
break;
137+
}
138+
} else if (SystemCoreClock == 48000000) {
139+
// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
140+
switch (hz) {
141+
case 100000:
142+
I2cHandle.Init.Timing = 0x20A03E55; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
143+
break;
144+
case 400000:
145+
I2cHandle.Init.Timing = 0x10800C21; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
146+
break;
147+
case 1000000:
148+
I2cHandle.Init.Timing = 0x00500816; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
149+
break;
150+
default:
151+
break;
152+
}
153+
}
154+
155+
// Enable the Fast Mode Plus capability
156+
if (hz == 1000000) {
157+
if (obj->i2c == I2C_1) {
158+
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1);
159+
}
160+
#if defined(I2C2_BASE)
161+
if (obj->i2c == I2C_2) {
162+
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2);
163+
}
164+
#endif
165+
#if defined(I2C3_BASE)
166+
if (obj->i2c == I2C_3) {
167+
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3);
168+
}
169+
#endif
133170
}
134171

172+
135173
// I2C configuration
136174
I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
137175
I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;

0 commit comments

Comments
 (0)