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[NUC472/M453] Disable GPIO IRQ debounce by default
Some application requires GPIO IRQ to be low latency. To complement it, open up GPIO IRQ debounce configuration through mbed_lib.json.
1 parent ef36f2f commit 107d633

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4 files changed

+87
-9
lines changed

4 files changed

+87
-9
lines changed

‎hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
{
2+
"name": "M451",
3+
"config": {
4+
"gpio-irq-debounce-enable": {
5+
"help": "Enable GPIO IRQ debounce",
6+
"value": 0
7+
},
8+
"gpio-irq-debounce-clock-source": {
9+
"help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
10+
"value": "GPIO_DBCTL_DBCLKSRC_LIRC"
11+
},
12+
13+
"gpio-irq-debounce-sample-rate": {
14+
"help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
15+
"value": "GPIO_DBCTL_DBCLKSEL_16"
16+
}
17+
}
18+
}

‎hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
{
2+
"name": "NUC472",
3+
"config": {
4+
"gpio-irq-debounce-enable": {
5+
"help": "Enable GPIO IRQ debounce",
6+
"value": 0
7+
},
8+
"gpio-irq-debounce-clock-source": {
9+
"help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
10+
"value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
11+
},
12+
13+
"gpio-irq-debounce-sample-rate": {
14+
"help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
15+
"value": "GPIO_DBCTL_DBCLKSEL_16"
16+
}
17+
}
18+
}

‎targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,24 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
5252

5353
#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
5454

55+
#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
56+
#define M451_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
57+
#else
58+
#define M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
59+
#endif
60+
61+
#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
62+
#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
63+
#else
64+
#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
65+
#endif
66+
67+
#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
68+
#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
69+
#else
70+
#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
71+
#endif
72+
5573
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
5674
{
5775
if (pin == NC) {
@@ -68,14 +86,19 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
6886
obj->irq_handler = (uint32_t) handler;
6987
obj->irq_id = id;
7088

89+
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
7190
//gpio_set(pin);
7291

92+
#if M451_GPIO_IRQ_DEBOUNCE_ENABLE
7393
// Configure de-bounce clock source and sampling cycle time
74-
GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_16);
94+
GPIO_SET_DEBOUNCE_TIME(M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
95+
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
96+
#else
97+
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
98+
#endif
7599

76100
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
77101

78-
MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
79102
var->obj_arr[pin_index] = obj;
80103

81104
// NOTE: InterruptIn requires IRQ enabled by default.
@@ -106,7 +129,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
106129
switch (event) {
107130
case IRQ_RISE:
108131
if (enable) {
109-
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
110132
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
111133
}
112134
else {
@@ -116,7 +138,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
116138

117139
case IRQ_FALL:
118140
if (enable) {
119-
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
120141
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
121142
}
122143
else {

‎targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c

Lines changed: 26 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,24 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
5858

5959
#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
6060

61+
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
62+
#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
63+
#else
64+
#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
65+
#endif
66+
67+
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
68+
#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
69+
#else
70+
#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
71+
#endif
72+
73+
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
74+
#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
75+
#else
76+
#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
77+
#endif
78+
6179
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
6280
{
6381
if (pin == NC) {
@@ -74,14 +92,19 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
7492
obj->irq_handler = (uint32_t) handler;
7593
obj->irq_id = id;
7694

95+
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
7796
//gpio_set(pin);
7897

98+
#if NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
7999
// Configure de-bounce clock source and sampling cycle time
80-
GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_IRC10K, GPIO_DBCTL_DBCLKSEL_16);
81-
100+
GPIO_SET_DEBOUNCE_TIME(NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
101+
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
102+
#else
103+
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
104+
#endif
105+
82106
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
83107

84-
MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
85108
var->obj_arr[pin_index] = obj;
86109

87110
// NOTE: InterruptIn requires IRQ enabled by default.
@@ -112,7 +135,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
112135
switch (event) {
113136
case IRQ_RISE:
114137
if (enable) {
115-
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
116138
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
117139
}
118140
else {
@@ -122,7 +144,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
122144

123145
case IRQ_FALL:
124146
if (enable) {
125-
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
126147
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
127148
}
128149
else {

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