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jeromecoutantjeromecoutant
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STM32 EMAC : more configurable
- PHY default configuration can be changed - AutoNegotiation - Speed - DuplexMode - PHY register offset can be updated depending on chosen PHY All unused parameters are cleaned.
1 parent c2c6d25 commit 1b40076

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6 files changed

+120
-164
lines changed

6 files changed

+120
-164
lines changed

‎features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,37 @@
33
"config": {
44
"eth-rxbufnb": 4,
55
"eth-txbufnb": 4,
6-
"eth-phyaddr": {
6+
"eth-phy-address": {
77
"help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)",
88
"value" : 0
9+
},
10+
"eth-phy-AutoNegotiation": {
11+
"help" : "Selects AutoNegotiation mode : ETH_AUTONEGOTIATION_ENABLE / ETH_AUTONEGOTIATION_DISABLE",
12+
"value" : "ETH_AUTONEGOTIATION_ENABLE"
13+
},
14+
"eth-phy-DuplexMode": {
15+
"help" : "Selects DuplexMode mode : ETH_MODE_FULLDUPLEX / ETH_MODE_HALFDUPLEX",
16+
"value" : "ETH_MODE_FULLDUPLEX"
17+
},
18+
"eth-phy-Speed": {
19+
"help" : "Selects Speed mode : ETH_SPEED_100M / ETH_SPEED_10M",
20+
"value" : "ETH_SPEED_100M"
21+
},
22+
"eth-phy-reset-delay": {
23+
"help" : "Reset process time - Default value: 0.5s as specified in LAN8742A datasheet",
24+
"value" : "500"
25+
},
26+
"eth-phy-status-register": {
27+
"help" : "PHY register Offset with auto-negotiation result - Default value is LAN8742A PHY Special Control/Status Register",
28+
"value" : "31"
29+
},
30+
"eth-phy-speed-status": {
31+
"help" : "Speed mask information in eth-phy-status-register",
32+
"value" : "0x0004"
33+
},
34+
"eth-phy-duplex-status": {
35+
"help" : "Duplex mask information in eth-phy-status-register",
36+
"value" : "0x0010"
937
}
1038
},
1139
"target_overrides": {
@@ -14,7 +42,7 @@
1442
"eth-txbufnb": 4
1543
},
1644
"ARCH_MAX": {
17-
"eth-phyaddr": 1
45+
"eth-phy-address": 1
1846
}
1947
}
2048
}

‎features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,6 @@
4343
#define THREAD_PRIORITY (osPriorityHigh)
4444

4545
#define PHY_TASK_PERIOD_MS 200
46-
#define ETH_PHY_ADDRESS MBED_CONF_STM32_EMAC_ETH_PHYADDR
4746

4847
#define STM_HWADDR_SIZE (6)
4948
#define STM_ETH_MTU_SIZE 1500
@@ -279,10 +278,10 @@ bool STM32_EMAC::low_level_init_successful()
279278
/* Init ETH */
280279
uint8_t MACAddr[6];
281280
EthHandle.Instance = ETH;
282-
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
283-
EthHandle.Init.Speed = ETH_SPEED_100M;
284-
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
285-
EthHandle.Init.PhyAddress = ETH_PHY_ADDRESS;
281+
EthHandle.Init.AutoNegotiation = MBED_CONF_STM32_EMAC_ETH_PHY_AUTONEGOTIATION;
282+
EthHandle.Init.Speed = MBED_CONF_STM32_EMAC_ETH_PHY_SPEED;
283+
EthHandle.Init.DuplexMode = MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEXMODE;
284+
EthHandle.Init.PhyAddress = MBED_CONF_STM32_EMAC_ETH_PHY_ADDRESS;
286285
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
287286
MACAddr[0] = MBED_MAC_ADDR_0;
288287
MACAddr[1] = MBED_MAC_ADDR_1;

‎features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
11
/* Copyright (c) 2017 ARM Limited
2+
* Copyright (c) 2017 STMicroelectronics
3+
* SPDX-License-Identifier: Apache-2.0
24
*
35
* Licensed under the Apache License, Version 2.0 (the "License");
46
* you may not use this file except in compliance with the License.
@@ -176,4 +178,4 @@ class STM32_EMAC : public EMAC {
176178
int phy_task_handle; /**< Handle for phy task event */
177179
};
178180

179-
#endif /* K64F_EMAC_H_ */
181+
#endif /* STM32_EMAC_H_ */

‎targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h

Lines changed: 31 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -162,75 +162,52 @@
162162

163163
/* ################## Ethernet peripheral configuration ##################### */
164164

165-
/* Section 1 : Ethernet peripheral configuration */
166-
167-
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
168-
#define MAC_ADDR0 2U
169-
#define MAC_ADDR1 0U
170-
#define MAC_ADDR2 0U
171-
#define MAC_ADDR3 0U
172-
#define MAC_ADDR4 0U
173-
#define MAC_ADDR5 0U
174-
175-
/* Definition of the Ethernet driver buffers size and count */
176-
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
177-
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
165+
/* Definition of the Ethernet driver buffers size and count */
166+
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
167+
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
178168

179169
#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
180-
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
181-
#endif
182-
183-
#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
184-
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
170+
/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
171+
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
172+
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
173+
#else
174+
/* ex: bare metal profile */
175+
#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
176+
#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
185177
#endif
186178

187179
/* Section 2: PHY configuration section */
188180

189-
/* DP83848 PHY Address*/
190-
#define DP83848_PHY_ADDRESS 0x01U
191-
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
192-
#define PHY_RESET_DELAY 0x000000FFU
193-
/* PHY Configuration delay */
181+
/* PHY delay */
182+
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
183+
#define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
184+
#else
185+
#define PHY_RESET_DELAY 0
186+
#endif
194187
#define PHY_CONFIG_DELAY 0x00000FFFU
195-
196188
#define PHY_READ_TO 0x0000FFFFU
197189
#define PHY_WRITE_TO 0x0000FFFFU
198190

199191
/* Section 3: Common PHY Registers */
200192

201-
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
202-
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
193+
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
194+
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
203195

204-
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
205-
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
206-
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
207-
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
208-
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
209-
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
210-
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
211-
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
212-
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
213-
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
214-
215-
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
216-
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
217-
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
196+
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
197+
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
198+
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
199+
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
218200

219201
/* Section 4: Extended PHY Registers */
220-
221-
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
222-
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
223-
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
224-
225-
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
226-
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
227-
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
228-
229-
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
230-
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
231-
232-
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
233-
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
202+
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
203+
#define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
204+
#define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
205+
#define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
206+
#else
207+
#define PHY_SR 0
208+
#define PHY_SPEED_STATUS 0
209+
#define PHY_DUPLEX_STATUS 0
210+
#endif
234211

235212
/* ################## SPI peripheral configuration ########################## */
236213

‎targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h

Lines changed: 30 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -170,75 +170,52 @@
170170

171171
/* ################## Ethernet peripheral configuration ##################### */
172172

173-
/* Section 1 : Ethernet peripheral configuration */
174-
175-
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
176-
#define MAC_ADDR0 2U
177-
#define MAC_ADDR1 0U
178-
#define MAC_ADDR2 0U
179-
#define MAC_ADDR3 0U
180-
#define MAC_ADDR4 0U
181-
#define MAC_ADDR5 0U
182-
183173
/* Definition of the Ethernet driver buffers size and count */
184174
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
185175
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
186176

187177
#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
188-
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
189-
#endif
190-
191-
#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
192-
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
178+
/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
179+
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
180+
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
181+
#else
182+
/* ex: bare metal profile */
183+
#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
184+
#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
193185
#endif
194186

195187
/* Section 2: PHY configuration section */
196188

197-
/* DP83848 PHY Address*/
198-
#define DP83848_PHY_ADDRESS 0x01U
199-
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
200-
#define PHY_RESET_DELAY 0x000000FFU
201-
/* PHY Configuration delay */
189+
/* PHY delay */
190+
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
191+
#define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
192+
#else
193+
#define PHY_RESET_DELAY 0
194+
#endif
202195
#define PHY_CONFIG_DELAY 0x00000FFFU
203-
204196
#define PHY_READ_TO 0x0000FFFFU
205197
#define PHY_WRITE_TO 0x0000FFFFU
206198

207199
/* Section 3: Common PHY Registers */
208200

209-
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
210-
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
211-
212-
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
213-
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
214-
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
215-
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
216-
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
217-
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
218-
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
219-
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
220-
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
221-
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
222-
223-
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
224-
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
225-
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
226-
201+
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
202+
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
203+
204+
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
205+
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
206+
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
207+
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
208+
227209
/* Section 4: Extended PHY Registers */
228-
229-
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
230-
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
231-
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
232-
233-
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
234-
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
235-
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
236-
237-
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
238-
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
239-
240-
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
241-
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
210+
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
211+
#define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
212+
#define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
213+
#define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
214+
#else
215+
#define PHY_SR 0
216+
#define PHY_SPEED_STATUS 0
217+
#define PHY_DUPLEX_STATUS 0
218+
#endif
242219

243220
/* ################## SPI peripheral configuration ########################## */
244221

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