Merge pull request #14808 from affrinpinhero-2356/i2cTimingPerformanceSolved

driver/i2c: STM32: I2C performance issue solved.

Author: 0xc0170

targets/TARGET_STM/README.md

@@ -408,6 +408,31 @@ You can change this in you local mbed_app.json:
 }
 ```
 
+#### I2C TIming calculation algorothm
+
+I2C drivers version 2 use I2C timing register.
+
+Enable I2C timing algorithm by setting the value of `i2c_timing_value_algo`
+target config to `true`
+
+```
+"i2c_timing_value_algo": {
+                "help": "If value was set to true I2C timing algorithm is 
+                enabled. Enabling may leads to performance issue. Keeping this
+                false and changing system clock will trigger assert.",
+                "value": false
+            }
+```
+Default configuration disables I2C timing algorithm. If user need to use
+different system clock speed other than default system clock configuration.
+Then I2C timing calculation algorithm need to enable. To enable
+
+```
+"i2c_timing_value_algo": {
+                "value": true
+            }
+```
+
 
 ### Sleep feature
 

targets/TARGET_STM/TARGET_STM32F0/i2c_device.c

@@ -41,7 +41,7 @@ uint32_t i2c_get_pclk(I2CName i2c)
                 pclk = HSI_VALUE;
                 break;
         }
-    } 
+    }
 #if defined I2C2_BASE
     else if (i2c == I2C_2) {
         pclk = HAL_RCC_GetSysClockFreq();
@@ -53,50 +53,4 @@ uint32_t i2c_get_pclk(I2CName i2c)
     }
     return pclk;
 }
-
-/**
- * @brief  Provide the suitable timing depending on requested frequency
- * @param  hz Required I2C clock in Hz.
- * @retval I2C timing or 0 in case of error.
- */
-uint32_t i2c_get_timing(I2CName i2c, int hz)
-{
-    uint32_t tim;
-    uint32_t pclk;
-
-    pclk = i2c_get_pclk(i2c);
-
-    if (pclk == I2C_PCLK_DEF) {
-        switch (hz) {
-            case 100000:
-                tim = TIMING_VAL_DEFAULT_CLK_100KHZ;
-                break;
-            case 400000:
-                tim = TIMING_VAL_DEFAULT_CLK_400KHZ;
-                break;
-            case 1000000:
-                tim = TIMING_VAL_DEFAULT_CLK_1MHZ;
-                break;
-            default:
-                MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
-                break;
-        }
-    }
-
-    else {
-        /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. 
-        User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. 
-        Enabling this may impact performance*/
-        MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO);
-#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
-        tim = i2c_compute_timing(pclk, hz);
-#endif
-    }
-    return tim;
-}
-
-/**
-  * @}
-  */
-
 #endif // DEVICE_I2C

targets/TARGET_STM/TARGET_STM32F0/i2c_device.h

@@ -37,18 +37,18 @@ extern "C" {
 /*  Define IP version */
 #define I2C_IP_VERSION_V2
 
-#define TIMING_VAL_DEFAULT_CLK_100KHZ  0x10805E89  // Standard mode with Rise Time = 400ns and Fall Time = 100ns
-#define TIMING_VAL_DEFAULT_CLK_400KHZ  0x00901850  // Fast mode with Rise Time = 250ns and Fall Time = 100ns
-#define TIMING_VAL_DEFAULT_CLK_1MHZ    0x00700818  // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
-#define I2C_PCLK_DEF                   48000000    // 48 MHz    
+#define TIMING_VAL_48M_CLK_100KHZ  0x10805E89  // Standard mode with Rise Time = 400ns and Fall Time = 100ns
+#define TIMING_VAL_48M_CLK_400KHZ  0x00901850  // Fast mode with Rise Time = 250ns and Fall Time = 100ns
+#define TIMING_VAL_48M_CLK_1MHZ    0x00700818  // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
+#define I2C_PCLK_48M               48000000    // 48 MHz    
 
 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
 
 /*  Family specifc settings for clock source */
 #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK
 
 uint32_t i2c_get_pclk(I2CName i2c);
-uint32_t i2c_get_timing(I2CName i2c, int hz);
+uint32_t i2c_get_timing(I2CName i2c, uint32_t current_timing, int current_hz, int hz);
 
 #if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
 uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq);

targets/TARGET_STM/TARGET_STM32F0/objects.h

@@ -94,6 +94,7 @@ struct i2c_s {
     uint32_t XferOperation;
     volatile uint8_t event;
     volatile int pending_start;
+    int current_hz;
 #if DEVICE_I2CSLAVE
     uint8_t slave;
     volatile uint8_t pending_slave_tx_master_rx;

targets/TARGET_STM/TARGET_STM32F3/i2c_device.c

@@ -76,65 +76,4 @@ uint32_t i2c_get_pclk(I2CName i2c)
     }
     return pclk;
 }
-
-/**
- * @brief  Provide the suitable timing depending on requested frequency
- * @param  hz Required I2C clock in Hz.
- * @retval I2C timing or 0 in case of error.
- */
-uint32_t i2c_get_timing(I2CName i2c, int hz)
-{
-    uint32_t tim;
-    uint32_t pclk;
-
-    pclk = i2c_get_pclk(i2c);
-
-    if (pclk == I2C_PCLK_HSI) {
-        switch (hz) {
-            case 100000:
-                tim = TIMING_VAL_64M_CLK_100KHZ;
-                break;
-            case 400000:
-                tim = TIMING_VAL_64M_CLK_400KHZ;
-                break;
-            case 1000000:
-                tim = TIMING_VAL_64M_CLK_1MHZ;
-                break;
-            default:
-                MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
-                break;
-        }
-    } else if (pclk == I2C_PCLK_HSE) {
-        switch (hz) {
-            case 100000:
-                tim = TIMING_VAL_72M_CLK_100KHZ;
-                break;
-            case 400000:
-                tim = TIMING_VAL_72M_CLK_400KHZ;
-                break;
-            case 1000000:
-                tim = TIMING_VAL_72M_CLK_1MHZ;
-                break;
-            default:
-                MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
-                break;
-        }
-    }
-
-    else {
-        /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. 
-        User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. 
-        Enabling this may impact performance*/
-        MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO);
-#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
-        tim = i2c_compute_timing(pclk, hz);
-#endif
-    }
-    return tim;
-}
-
-/**
-  * @}
-  */
-
 #endif // DEVICE_I2C

targets/TARGET_STM/TARGET_STM32F3/i2c_device.h

@@ -43,12 +43,12 @@ extern "C" {
 #define TIMING_VAL_64M_CLK_100KHZ  0x10B17DB4  // Standard mode with Rise time = 120ns, Fall time = 120ns
 #define TIMING_VAL_64M_CLK_400KHZ  0x00E22163  // Fast Mode with Rise time = 120ns, Fall time = 120ns
 #define TIMING_VAL_64M_CLK_1MHZ    0x00A00D1E  // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
-#define I2C_PCLK_HSI               64000000    // 64 MHz
+#define I2C_PCLK_64M               64000000    // 64 MHz
 
 #define TIMING_VAL_72M_CLK_100KHZ  0x10D28DCB  // Standard mode with Rise time = 120ns, Fall time = 120ns
 #define TIMING_VAL_72M_CLK_400KHZ  0x00F32571  // Fast Mode with Rise time = 120ns, Fall time = 120ns
 #define TIMING_VAL_72M_CLK_1MHZ    0x00C00D24  // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
-#define I2C_PCLK_HSE               72000000    // 72 MHz
+#define I2C_PCLK_72M               72000000    // 72 MHz
 
 
 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
@@ -62,7 +62,7 @@ extern "C" {
 #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK
 
 uint32_t i2c_get_pclk(I2CName i2c);
-uint32_t i2c_get_timing(I2CName i2c, int hz);
+uint32_t i2c_get_timing(I2CName i2c, uint32_t current_timing, int current_hz, int hz);
 
 #if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
 uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq);

targets/TARGET_STM/TARGET_STM32F3/objects.h

@@ -109,6 +109,7 @@ struct i2c_s {
     uint32_t XferOperation;
     volatile uint8_t event;
     volatile int pending_start;
+    int current_hz;
 #if DEVICE_I2CSLAVE
     uint8_t slave;
     volatile uint8_t pending_slave_tx_master_rx;

targets/TARGET_STM/TARGET_STM32F7/i2c_device.c

@@ -106,45 +106,4 @@ uint32_t i2c_get_pclk(I2CName i2c)
     }
     return pclk;
 }
-
-/**
- * @brief  Provide the suitable timing depending on requested frequency
- * @param  hz Required I2C clock in Hz.
- * @retval I2C timing or 0 in case of error.
- */
-uint32_t i2c_get_timing(I2CName i2c, int hz)
-{
-    uint32_t tim;
-    uint32_t pclk;
-    pclk = i2c_get_pclk(i2c);
-    if (pclk == I2C_PCLK_DEF) {
-        switch (hz) {
-            case 100000:
-                tim = TIMING_VAL_DEFAULT_CLK_100KHZ;
-                break;
-            case 400000:
-                tim = TIMING_VAL_DEFAULT_CLK_400KHZ;
-                break;
-            case 1000000:
-                tim = TIMING_VAL_DEFAULT_CLK_1MHZ;
-                break;
-            default:
-                MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
-                break;
-        }
-    } else {
-        /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. 
-        User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. 
-        Enabling this may impact performance*/
-        MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO);
-#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
-        tim = i2c_compute_timing(pclk, hz);
-#endif
-    }
-    return tim;
-}
-
-/**
-  * @}
-  */
 #endif // DEVICE_I2C

targets/TARGET_STM/TARGET_STM32F7/i2c_device.h

@@ -40,10 +40,10 @@ extern "C" {
 /*  Define I2C Device */
 #if DEVICE_I2C
 
-#define TIMING_VAL_DEFAULT_CLK_100KHZ  0x10916998  // Standard mode with Rise time = 120ns, Fall time = 120ns
-#define TIMING_VAL_DEFAULT_CLK_400KHZ  0x00B11B54  // Fast Mode with Rise time = 120ns, Fall time = 120ns
-#define TIMING_VAL_DEFAULT_CLK_1MHZ    0x0090091B  // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
-#define I2C_PCLK_DEF                   54000000    // 54 MHz
+#define TIMING_VAL_54M_CLK_100KHZ  0x10916998  // Standard mode with Rise time = 120ns, Fall time = 120ns
+#define TIMING_VAL_54M_CLK_400KHZ  0x00B11B54  // Fast Mode with Rise time = 120ns, Fall time = 120ns
+#define TIMING_VAL_54M_CLK_1MHZ    0x0090091B  // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
+#define I2C_PCLK_54M               54000000    // 54 MHz
 
 /*  Define IP version */
 #define I2C_IP_VERSION_V2
@@ -57,7 +57,7 @@ extern "C" {
 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_PCLK1
 
 uint32_t i2c_get_pclk(I2CName i2c);
-uint32_t i2c_get_timing(I2CName i2c, int hz);
+uint32_t i2c_get_timing(I2CName i2c, uint32_t current_timing, int current_hz, int hz);
 
 #if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO
 uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq);

targets/TARGET_STM/TARGET_STM32F7/objects.h

@@ -125,6 +125,7 @@ struct i2c_s {
     uint32_t XferOperation;
     volatile uint8_t event;
     volatile int pending_start;
+    int current_hz;
 #if DEVICE_I2CSLAVE
     uint8_t slave;
     volatile uint8_t pending_slave_tx_master_rx;