@@ -137,7 +137,9 @@ extern "C" {
137
137
SHCI_OCF_C2_REINIT ,
138
138
SHCI_OCF_C2_ZIGBEE_INIT ,
139
139
SHCI_OCF_C2_LLD_TESTS_INIT ,
140
- SHCI_OCF_C2_EXTPA_CONFIG
140
+ SHCI_OCF_C2_EXTPA_CONFIG ,
141
+ SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL ,
142
+ SHCI_OCF_C2_LLD_BLE_INIT
141
143
} SHCI_OCF_t ;
142
144
143
145
#define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
@@ -296,6 +298,20 @@ extern "C" {
296
298
297
299
#define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)
298
300
/** Command parameters */
301
+ typedef PACKED_STRUCT
302
+ {
303
+ uint8_t thread_config ;
304
+ uint8_t ble_config ;
305
+ uint8_t mac_802_15_4_config ;
306
+ uint8_t zigbee_config ;
307
+ } SHCI_C2_DEBUG_TracesConfig_t ;
308
+
309
+ typedef PACKED_STRUCT
310
+ {
311
+ uint8_t ble_dtb_cfg ;
312
+ uint8_t reserved [3 ];
313
+ } SHCI_C2_DEBUG_GeneralConfig_t ;
314
+
299
315
typedef PACKED_STRUCT {
300
316
uint8_t * pGpioConfig ;
301
317
uint8_t * pTracesConfig ;
@@ -352,6 +368,8 @@ extern "C" {
352
368
353
369
#define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT)
354
370
371
+ #define SHCI_OPCODE_C2_LLD_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_BLE_INIT)
372
+
355
373
#define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG)
356
374
/** Command parameters */
357
375
enum
@@ -375,6 +393,16 @@ extern "C" {
375
393
376
394
/** No response parameters*/
377
395
396
+ #define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)
397
+ /** Command parameters */
398
+ typedef enum
399
+ {
400
+ FLASH_ACTIVITY_CONTROL_PES ,
401
+ FLASH_ACTIVITY_CONTROL_SEM7 ,
402
+ }SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t ;
403
+
404
+ /** No response parameters*/
405
+
378
406
/* Exported type --------------------------------------------------------*/
379
407
380
408
typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t ;
@@ -427,16 +455,21 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
427
455
#define INFO_STACK_TYPE_MASK 0x000000ff
428
456
#define INFO_STACK_TYPE_NONE 0
429
457
430
- #define INFO_STACK_TYPE_BLE_STANDARD 0x1
431
- #define INFO_STACK_TYPE_BLE_HCI 0x2
458
+ #define INFO_STACK_TYPE_BLE_STANDARD 0x01
459
+ #define INFO_STACK_TYPE_BLE_HCI 0x02
460
+ #define INFO_STACK_TYPE_BLE_LIGHT 0x03
432
461
#define INFO_STACK_TYPE_THREAD_FTD 0x10
433
462
#define INFO_STACK_TYPE_THREAD_MTD 0x11
434
- #define INFO_STACK_TYPE_ZIGBEE 0x30
463
+ #define INFO_STACK_TYPE_ZIGBEE_FFD 0x30
464
+ #define INFO_STACK_TYPE_ZIGBEE_RFD 0x31
435
465
#define INFO_STACK_TYPE_MAC 0x40
436
466
#define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50
437
467
#define INFO_STACK_TYPE_802154_LLD_TESTS 0x60
438
468
#define INFO_STACK_TYPE_802154_PHY_VALID 0x61
439
469
#define INFO_STACK_TYPE_BLE_PHY_VALID 0x62
470
+ #define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63
471
+ #define INFO_STACK_TYPE_BLE_RLV 0x64
472
+ #define INFO_STACK_TYPE_802154_RLV 0x65
440
473
#define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70
441
474
442
475
typedef struct {
@@ -587,6 +620,16 @@ typedef struct {
587
620
*/
588
621
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init ( uint8_t param_size , uint8_t * p_param );
589
622
623
+ /**
624
+ * SHCI_C2_LLD_BLE_Init
625
+ * @brief Starts the LLD tests CLI
626
+ *
627
+ * @param param_size : Nb of bytes
628
+ * @param p_param : pointeur with data to give from M4 to M0
629
+ * @retval Status
630
+ */
631
+ SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init ( uint8_t param_size , uint8_t * p_param );
632
+
590
633
/**
591
634
* SHCI_C2_ZIGBEE_Init
592
635
* @brief Starts the Zigbee Stack
@@ -706,6 +749,18 @@ typedef struct {
706
749
*/
707
750
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig (uint32_t gpio_port , uint16_t gpio_pin_number , uint8_t gpio_polarity , uint8_t gpio_status );
708
751
752
+ /**
753
+ * SHCI_C2_SetFlashActivityControl
754
+ * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash
755
+ *
756
+ * @param Source: It can be one of the following list
757
+ * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash
758
+ * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash.
759
+ * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash.
760
+ *
761
+ * @retval Status
762
+ */
763
+ SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl (SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source );
709
764
710
765
#ifdef __cplusplus
711
766
}
0 commit comments