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Fix setting the QE bit on ISSI Flash memories
By default QSPIFBlockDevice assumes a Flash memory have two Status registers and when writing the Status registers it writes 2 bytes using the WRSR instruction. This will not work on a ISSI Flash memory as they only have a single status register and attempting to write two bytes using WRSR will cause it to ignore the request and be unable to set the QE bit. ISSI datasheet specifies that the WRSR instruction only write a single byte so override the number of status registers for ISSI Flash memories.
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components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp

Lines changed: 17 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,6 +1062,11 @@ int QSPIFBlockDevice::_handle_vendor_quirks()
10621062
_read_status_reg_2_inst = QSPIF_INST_RDCR;
10631063
_attempt_4_byte_addressing = false;
10641064
break;
1065+
case 0x9d:
1066+
// ISSI devices have only one status register
1067+
tr_debug("Applying quirks for ISSI");
1068+
_num_status_registers = 1;
1069+
break;
10651070
}
10661071

10671072
return 0;
@@ -1420,17 +1425,19 @@ qspi_status_t QSPIFBlockDevice::_qspi_read_status_registers(uint8_t *reg_buffer)
14201425

14211426
// Read Status Register 2 (and beyond, if applicable)
14221427
unsigned int read_length = _num_status_registers - 1; // We already read status reg 1 above
1423-
status = _qspi_send_general_command(_read_status_reg_2_inst, QSPI_NO_ADDRESS_COMMAND,
1424-
NULL, 0,
1425-
(char *) &reg_buffer[1], read_length);
1426-
if (QSPI_STATUS_OK == status) {
1427-
tr_debug("Reading Status Register 2 Success: value = 0x%x", (int) reg_buffer[1]);
1428-
if (_num_status_registers > 2) {
1429-
tr_debug("Reading Register 3 Success: value = 0x%x", (int) reg_buffer[2]);
1428+
if (read_length > 0) {
1429+
status = _qspi_send_general_command(_read_status_reg_2_inst, QSPI_NO_ADDRESS_COMMAND,
1430+
NULL, 0,
1431+
(char *) &reg_buffer[1], read_length);
1432+
if (QSPI_STATUS_OK == status) {
1433+
tr_debug("Reading Status Register 2 Success: value = 0x%x", (int) reg_buffer[1]);
1434+
if (_num_status_registers > 2) {
1435+
tr_debug("Reading Register 3 Success: value = 0x%x", (int) reg_buffer[2]);
1436+
}
1437+
} else {
1438+
tr_error("Reading Status Register 2 failed");
1439+
return status;
14301440
}
1431-
} else {
1432-
tr_error("Reading Status Register 2 failed");
1433-
return status;
14341441
}
14351442

14361443
return QSPI_STATUS_OK;

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